[PATCH net-next 04/21] net: stmmac: rk: group MACPHY register offset and fields together
From: Russell King (Oracle) <hidden>
Date: 2026-01-23 11:00:57
Also in:
linux-arm-kernel, linux-rockchip
Subsystem:
arm/rockchip soc support, networking drivers, stmmac ethernet driver, the rest · Maintainers:
Heiko Stuebner, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
Group the MACPHY register offsets and associated bitfields together to become self-documenting which definitions are associated with which register. Signed-off-by: Russell King (Oracle) <redacted> --- drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index c8b49ed2064a..5f8d2031b97c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c@@ -162,15 +162,17 @@ static int rk_set_clk_mac_speed(struct rk_priv_data *bsp_priv, ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) #define RK_GRF_MACPHY_CON0 0xb00 -#define RK_GRF_MACPHY_CON1 0xb04 -#define RK_GRF_MACPHY_CON2 0xb08 -#define RK_GRF_MACPHY_CON3 0xb0c - #define RK_MACPHY_ENABLE GRF_BIT(0) #define RK_MACPHY_DISABLE GRF_CLR_BIT(0) #define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) #define RK_GMAC2PHY_RMII_MODE GRF_FIELD(7, 6, 1) + +#define RK_GRF_MACPHY_CON1 0xb04 + +#define RK_GRF_MACPHY_CON2 0xb08 #define RK_GRF_CON2_MACPHY_ID GRF_FIELD(15, 0, 0x1234) + +#define RK_GRF_MACPHY_CON3 0xb0c #define RK_GRF_CON3_MACPHY_ID GRF_FIELD(5, 0, 0x35) static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
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2.47.3