[PATCH RFC 3/4] arm64: dts: s32: set Ethernet channel irqs
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STALE277d
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From: Jan Petrous via B4 Relay <devnull+jan.petrous.oss.nxp.com@kernel.org>
Date: 2025-12-14 22:15:53
Also in:
b4-sent, imx, linux-arm-kernel, linux-devicetree, lkml
Subsystem:
arm/freescale imx / mxc / layerscape arm architecture, arm/nxp s32g architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
Revision rfc of 12 in this series.
Revisions (12)
From: "Jan Petrous (OSS)" <jan.petrous@oss.nxp.com>
The GMAC Ethernet controller found on S32G2/S32G3 and S32R45
contains up to 5 RX and 5 TX channels.
It can operate in two interrupt modes:
1) Sharing irq mode: only one irq line is used
for all channels.
2) Multiple irq mode: every channel uses two irq lines,
one for RX and second for TX.
Specify all irq twins for all channels.
Signed-off-by: Jan Petrous (OSS) <jan.petrous@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/s32g2.dtsi | 24 ++++++++++++++++++++++--
arch/arm64/boot/dts/freescale/s32g3.dtsi | 24 ++++++++++++++++++++++--
2 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 51d00dac12de..ea615fc5ccd9 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi@@ -732,8 +732,28 @@ gmac0: ethernet@4033c000 { reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent = <&gic>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 0: tx, rx */ + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 1: tx, rx */ + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 2: tx, rx */ + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 3: tx, rx */ + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 4: tx, rx */ + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; status = "disabled";
diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
index eff7673e7f34..ecbec49c7344 100644
--- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi@@ -809,8 +809,28 @@ gmac0: ethernet@4033c000 { reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ interrupt-parent = <&gic>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "macirq"; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 0: tx, rx */ + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 1: tx, rx */ + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 2: tx, rx */ + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 3: tx, rx */ + <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + /* CHN 4: tx, rx */ + <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "tx-queue-0", "rx-queue-0", + "tx-queue-1", "rx-queue-1", + "tx-queue-2", "rx-queue-2", + "tx-queue-3", "rx-queue-3", + "tx-queue-4", "rx-queue-4"; snps,mtl-rx-config = <&mtl_rx_setup>; snps,mtl-tx-config = <&mtl_tx_setup>; status = "disabled";
--
2.47.0