[PATCH net-next v4 2/4] ARM: dts: aspeed-g6: Add scu and rgmii delay value per step for MAC
From: Jacky Chou <jacky_chou@aspeedtech.com>
Date: 2025-11-10 11:10:10
Also in:
linux-arm-kernel, linux-aspeed, linux-devicetree, lkml
Subsystem:
arm/aspeed machine support, the rest · Maintainers:
Joel Stanley, Andrew Jeffery, Linus Torvalds
The RGMII delay is configured in SCU region in Aspeed AST2600, therefore, add aspeed,scu property in dtsi for rgmii delay. And the RGMII delay value in each MAC is different. List below: MAC0 and MAC1 -> 45 ps MAC2 and MAC3 -> 250 ps Add "aspeed,rgmii-delay-ps" property for each MAC to specify the corresponding delay value. Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com> --- arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index f8662c8ac089..2c71e691c547 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi@@ -236,6 +236,8 @@ mac0: ethernet@1e660000 { reg = <0x1e660000 0x180>; interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>; + aspeed,scu = <&syscon>; + aspeed,rgmii-delay-ps = <45>; status = "disabled"; };
@@ -244,6 +246,8 @@ mac1: ethernet@1e680000 { reg = <0x1e680000 0x180>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>; + aspeed,scu = <&syscon>; + aspeed,rgmii-delay-ps = <45>; status = "disabled"; };
@@ -252,6 +256,8 @@ mac2: ethernet@1e670000 { reg = <0x1e670000 0x180>; interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>; + aspeed,scu = <&syscon>; + aspeed,rgmii-delay-ps = <250>; status = "disabled"; };
@@ -260,6 +266,8 @@ mac3: ethernet@1e690000 { reg = <0x1e690000 0x180>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>; + aspeed,scu = <&syscon>; + aspeed,rgmii-delay-ps = <250>; status = "disabled"; };
--
2.34.1