On Tue, 14 Oct 2025 22:35:25 +0800, Luo Jie wrote:

The NSS clock controller on the IPQ5424 SoC provides clocks and resets
to the networking related hardware blocks such as the Packet Processing
Engine (PPE) and UNIPHY (PCS). Its parent clocks are sourced from the
GCC, CMN PLL, and UNIPHY blocks.

Additionally, register the gpll0_out_aux GCC clock, which serves as one
of the parent clocks for some of the NSS clocks.

[...]

Applied, thanks!

[01/10] clk: qcom: gcc-ipq5424: Correct the icc_first_node_id
        commit: 464ce94531f5a62ce29081a9d3c70eb4d525f443
[04/10] clk: qcom: gcc-ipq5424: Enable NSS NoC clocks to use icc-clk
        commit: e2cf3b73573e24283e1c640eb9a186cfe3c01d84
[06/10] clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock
        commit: d08882c66d7a929c321cfaca9dee64e40eba3bd2
[08/10] clk: qcom: Add NSS clock controller driver for IPQ5424
        commit: fd0b632efbbdf427678a7a880abeb828bc4633fe

Best regards,
-- 
Bjorn Andersson [off-list ref]