[PATCH v5 06/10] clk: qcom: gcc-ipq5424: Add gpll0_out_aux clock
From: Luo Jie <quic_luoj@quicinc.com>
Date: 2025-09-09 13:41:16
Also in:
linux-arm-kernel, linux-arm-msm, linux-clk, linux-devicetree, linux-pm, lkml
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Bjorn Andersson, Linus Torvalds
The clock gpll0_out_aux acts as the parent clock for some of the NSS (Network Subsystem) clocks. Reviewed-by: Konrad Dybcio <redacted> Signed-off-by: Luo Jie <quic_luoj@quicinc.com> --- drivers/clk/qcom/gcc-ipq5424.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
index 6cfe4f2b2888..35af6ffeeb85 100644
--- a/drivers/clk/qcom/gcc-ipq5424.c
+++ b/drivers/clk/qcom/gcc-ipq5424.c@@ -79,6 +79,20 @@ static struct clk_fixed_factor gpll0_div2 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0.clkr.hw + }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2 = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_NSS_HUAYRA],
@@ -2934,6 +2948,7 @@ static struct clk_regmap *gcc_ipq5424_clocks[] = { [GPLL2] = &gpll2.clkr, [GPLL2_OUT_MAIN] = &gpll2_out_main.clkr, [GPLL4] = &gpll4.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq5424_resets[] = {
--
2.34.1