Re: [PATCH v5 03/27] clk: mediatek: clk-mux: Add ops for mux gates with set/clr/upd and FENC
From: Chen-Yu Tsai <wenst@chromium.org>
Date: 2025-09-05 04:10:07
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
On Fri, Aug 29, 2025 at 5:20 PM Laura Nao [off-list ref] wrote:
MT8196 uses set/clr/upd registers for mux gate enable/disable control, along with a FENC bit to check the status. Add new set of mux gate clock operations with support for set/clr/upd and FENC status logic. Reviewed-by: Nícolas F. R. A. Prado <redacted> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <redacted>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>