On 24/06/2025 16:32, Laura Nao wrote:

+  '#reset-cells':
+    const: 1
+    description:
+      Reset lines for PEXTP0/1 and UFS blocks.
+
+  mediatek,hardware-voter:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      On the MT8196 SoC, a Hardware Voter (HWV) backed by a fixed-function
+      MCU manages clock and power domain control across the AP and other
+      remote processors. By aggregating their votes, it ensures clocks are
+      safely enabled/disabled and power domains are active before register
+      access.

Resource voting is not via any phandle, but either interconnects or
required opps for power domain.

I already commented on this, so don't send v3 with the same.

Best regards,
Krzysztof