[PATCH 30/30] clk: mediatek: mt8196: Add UFS and PEXTP0/1 reset controllers
From: Laura Nao <hidden>
Date: 2025-06-23 10:31:08
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-mediatek, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Linus Torvalds
From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Add definitions to register the reset controllers found in the UFS and PEXTP clock controllers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Laura Nao <redacted> --- drivers/clk/mediatek/clk-mt8196-pextp.c | 36 ++++++++++++++++++++++++ drivers/clk/mediatek/clk-mt8196-ufs_ao.c | 25 ++++++++++++++++ 2 files changed, 61 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8196-pextp.c b/drivers/clk/mediatek/clk-mt8196-pextp.c
index 938100e4836b..9a7623bf2b1c 100644
--- a/drivers/clk/mediatek/clk-mt8196-pextp.c
+++ b/drivers/clk/mediatek/clk-mt8196-pextp.c@@ -6,6 +6,7 @@ * Laura Nao <laura.nao@collabora.com> */ #include <dt-bindings/clock/mediatek,mt8196-clock.h> +#include <dt-bindings/reset/mediatek,mt8196-resets.h> #include <linux/clk-provider.h> #include <linux/module.h> #include <linux/of_device.h>
@@ -13,6 +14,9 @@ #include "clk-gate.h" #include "clk-mtk.h" +#include "reset.h" + +#define MT8196_PEXTP_RST0_SET_OFFSET 0x8 static const struct mtk_gate_regs pext_cg_regs = { .set_ofs = 0x18,
@@ -41,9 +45,25 @@ static const struct mtk_gate pext_clks[] = { GATE_PEXT(CLK_PEXT_PEXTP_VLP_AO_P0_LP, "pext_pextp_vlp_ao_p0_lp", "clk26m", 19), }; +static u16 pext_rst_ofs[] = { MT8196_PEXTP_RST0_SET_OFFSET }; + +static u16 pext_rst_idx_map[] = { + [MT8196_PEXTP0_RST0_PCIE0_MAC] = 0, + [MT8196_PEXTP0_RST0_PCIE0_PHY] = 1, +}; + +static const struct mtk_clk_rst_desc pext_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = pext_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pext_rst_ofs), + .rst_idx_map = pext_rst_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(pext_rst_idx_map), +}; + static const struct mtk_clk_desc pext_mcd = { .clks = pext_clks, .num_clks = ARRAY_SIZE(pext_clks), + .rst_desc = &pext_rst_desc, }; static const struct mtk_gate pext1_clks[] = {
@@ -69,9 +89,25 @@ static const struct mtk_gate pext1_clks[] = { GATE_PEXT(CLK_PEXT1_PEXTP_VLP_AO_P2_LP, "pext1_pextp_vlp_ao_p2_lp", "clk26m", 27), }; +static u16 pext1_rst_idx_map[] = { + [MT8196_PEXTP1_RST0_PCIE1_MAC] = 0, + [MT8196_PEXTP1_RST0_PCIE1_PHY] = 1, + [MT8196_PEXTP1_RST0_PCIE2_MAC] = 8, + [MT8196_PEXTP1_RST0_PCIE2_PHY] = 9, +}; + +static const struct mtk_clk_rst_desc pext1_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = pext_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(pext_rst_ofs), + .rst_idx_map = pext1_rst_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(pext1_rst_idx_map), +}; + static const struct mtk_clk_desc pext1_mcd = { .clks = pext1_clks, .num_clks = ARRAY_SIZE(pext1_clks), + .rst_desc = &pext1_rst_desc, }; static const struct of_device_id of_match_clk_mt8196_pextp[] = {
diff --git a/drivers/clk/mediatek/clk-mt8196-ufs_ao.c b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c
index 49f4f4af7f41..858706b3ba6f 100644
--- a/drivers/clk/mediatek/clk-mt8196-ufs_ao.c
+++ b/drivers/clk/mediatek/clk-mt8196-ufs_ao.c@@ -6,6 +6,7 @@ * Laura Nao <laura.nao@collabora.com> */ #include <dt-bindings/clock/mediatek,mt8196-clock.h> +#include <dt-bindings/reset/mediatek,mt8196-resets.h> #include <linux/clk-provider.h> #include <linux/module.h> #include <linux/of_device.h>
@@ -14,6 +15,9 @@ #include "clk-gate.h" #include "clk-mtk.h" +#define MT8196_UFSAO_RST0_SET_OFFSET 0x48 +#define MT8196_UFSAO_RST1_SET_OFFSET 0x148 + static const struct mtk_gate_regs ufsao0_cg_regs = { .set_ofs = 0x108, .clr_ofs = 0x10c,
@@ -59,9 +63,30 @@ static const struct mtk_gate ufsao_clks[] = { GATE_UFSAO1(CLK_UFSAO_PHY_SAP, "ufsao_phy_sap", "clk26m", 8), }; +static u16 ufsao_rst_ofs[] = { + MT8196_UFSAO_RST0_SET_OFFSET, + MT8196_UFSAO_RST1_SET_OFFSET +}; + +static u16 ufsao_rst_idx_map[] = { + [MT8196_UFSAO_RST0_UFS_MPHY] = 8, + [MT8196_UFSAO_RST1_UFS_UNIPRO] = 1 * RST_NR_PER_BANK + 0, + [MT8196_UFSAO_RST1_UFS_CRYPTO] = 1 * RST_NR_PER_BANK + 1, + [MT8196_UFSAO_RST1_UFSHCI] = 1 * RST_NR_PER_BANK + 2, +}; + +static const struct mtk_clk_rst_desc ufsao_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = ufsao_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(ufsao_rst_ofs), + .rst_idx_map = ufsao_rst_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(ufsao_rst_idx_map), +}; + static const struct mtk_clk_desc ufsao_mcd = { .clks = ufsao_clks, .num_clks = ARRAY_SIZE(ufsao_clks), + .rst_desc = &ufsao_rst_desc, }; static const struct of_device_id of_match_clk_mt8196_ufs_ao[] = {
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