Re: [PATCH v9 03/27] cxl: add capabilities field to cxl_dev_state and cxl_port

Alejandro Lucero Palau wrote:
[..]

quoted

I do not understand the rationale for a capability bitmap. There is
already a 'valid' flag in 'struct cxl_reg_map' for all register blocks.
Any optional core functionality should key off those existing flags.

The current code is based on Type3 and the registers and capabilities 
are defined as mandatory, I think except RAS.

With Type2 we have optional capabilities like mailbox and hdm, and the 
code probing the regs should not make any assumption about what should 
be there.

With this patchset the capabilities to expect are set by the accel 
driver and compared with those discovered when probing CXL regs. 
Although the capabilities check could use the cxl_reg_map, I consider it 
is convenient to have a capability bitmap for keeping those discovered 
and easily checking them against those expected by the accel driver, and 
reporting them (if necessary) as well without further processing.

That is just on-loading redundancy to the core data structure for a
workalike way of checking the available register blocks. The 'struct
cxl_reg_map' already tracks this, the only needed change is to move the
responsibility for validating those bits to the driver. That work is
nearly identical to teaching the driver to inject a capability bitmask,
but more flexible for the case where the driver wants to optionally
enable functionality. In that latter case it will end up checking the
valid-bits anyway.