Re: [PATCH net-next v6] net: phy: intel-xway: Add RGMII internal delay configuration

On 2023-02-22 17:04, Michael Walle wrote:

Hi Tim, Hi Martin,

quoted

I've got some boards with the GPY111 phy on them and I'm finding that
modifying XWAY_MDIO_MIICTRL to change the skew has no effect unless I
do a soft reset (BCMR_RESET) first. I don't see anything in the
datasheet which specifies this to be the case so I'm interested it
what you have found. Are you sure adjusting the skews like this
without a soft (or hard pin based) reset actually works?

I do have the same PHY and I'm puzzled with the delay settings. Do
you have an EEPROM attached to the PHY? According to my datasheet,
that seems to make a difference. Apparently, only if there is an
EEPROM, you can change the value (the value is then also written to
the EEPROM according the datasheet).
If you don't have one, the values will get overwritten by the
external strappings on a soft reset. Therefore, it seems they cannot
be set. (FWIW there is also a sticky bit, but that doesn't seem to
help in this case).

-michael

Yes, you are right. The datasheet says: "In no-EEPROM mode, writing to
this register has no impact on operation of the device".

But changing this settings without an EEPROM indeed has an impact.

We don't use an EEPROM and without tuning this values some boards are
unable to communicate on the ethernet port(s).

I varied these values during operation in the uboot and was able to test
the limits very nicely.

I wouldn't have introduced this feature if it hasn't got any impact.

Regards,
Martin