Re: [PATCH 04/12] soc: sifive: ccache: Add non-coherent DMA handling
From: Conor Dooley <conor@kernel.org>
Date: 2023-02-16 18:50:36
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linux-arm-kernel, linux-devicetree, linux-riscv, lkml
Emil, +CC Daire On Sat, Feb 11, 2023 at 05:18:13AM +0200, Cristian Ciocaltea wrote:
From: Emil Renner Berthing <kernel@esmil.dk> Add functions to flush the caches and handle non-coherent DMA. Signed-off-by: Emil Renner Berthing <kernel@esmil.dk> [replace <asm/cacheflush.h> with <linux/cacheflush.h>] Signed-off-by: Cristian Ciocaltea <redacted> ---
+void *sifive_ccache_set_uncached(void *addr, size_t size)
+{
+ phys_addr_t phys_addr = __pa(addr) + uncached_offset;
+ void *mem_base;
+
+ mem_base = memremap(phys_addr, size, MEMREMAP_WT);
+ if (!mem_base) {
+ pr_err("%s memremap failed for addr %p\n", __func__, addr);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return mem_base;
+}The rest of this I either get b/c we did it, or will become moot so I amn't worried about it, but can you please explain this, in particular the memremap that you're doing here? Cheers, Conor.
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