[PATCH v3 08/19] ARM: dts: imx6dl-plym2m: configure ethernet reference clock parent
From: Oleksij Rempel <o.rempel@pengutronix.de>
Date: 2023-01-31 08:52:55
Also in:
linux-clk, linux-devicetree, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
On this board the PHY is the ref clock provider. So, configure ethernet reference clock as input. Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> --- arch/arm/boot/dts/imx6dl-plym2m.dts | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-plym2m.dts b/arch/arm/boot/dts/imx6dl-plym2m.dts
index 522660c912a0..e3c10483f33b 100644
--- a/arch/arm/boot/dts/imx6dl-plym2m.dts
+++ b/arch/arm/boot/dts/imx6dl-plym2m.dts@@ -84,6 +84,7 @@ clk50m_phy: phy-clock { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; + clock-output-names = "enet_ref_pad"; }; reg_3v3: regulator-3v3 {
@@ -173,6 +174,13 @@ &can1 { status = "okay"; }; +&clks { + clocks = <&clk50m_phy>; + clock-names = "enet_ref_pad"; + assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>; + assigned-clock-parents = <&clk50m_phy>; +}; + &ecspi1 { cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; pinctrl-names = "default";
@@ -254,10 +262,6 @@ &fec { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; - clocks = <&clks IMX6QDL_CLK_ENET>, - <&clks IMX6QDL_CLK_ENET>, - <&clk50m_phy>; - clock-names = "ipg", "ahb", "ptp"; phy-handle = <&rgmii_phy>; status = "okay";
--
2.30.2