Hi Andrew and Andreas,

On Thu, Nov 03, 2022 at 11:05:30PM +0100, Andrew Lunn wrote:

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+      - description: Main GMAC clock
+      - description: Peripheral registers clock
+      - description: Transmit SGMII clock
+      - description: Transmit RGMII clock
+      - description: Transmit RMII clock
+      - description: Transmit MII clock
+      - description: Receive SGMII clock
+      - description: Receive RGMII clock
+      - description: Receive RMII clock
+      - description: Receive MII clock
+      - description:
+          PTP reference clock. This clock is used for programming the
+          Timestamp Addend Register. If not passed then the system
+          clock will be used.

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Not clear to me has been whether the PHY mode can be switched at runtime
(like DPAA2 on Layerscape allows for SFPs) or whether this is fixed by board
design.

Does the hardware support 1000BaseX? Often the hardware implementing
SGMII can also do 1000BaseX, since SGMII is an extended/hacked up
1000BaseX.

If you have an SFP connected to the SERDES, a fibre module will want
1000BaseX and a copper module will want SGMII. phylink will tell you
what phy-mode you need to use depending on what module is in the
socket. This however might be a mute point, since both of these are
probably using the SGMII clocks.

Of the other MII modes listed, it is very unlikely a runtime swap will
occur.

	Andrew

Here I just focus on GMAC since there are other LAN interfaces that S32 family
uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
type used on S32G-EVB and S32G-RDB2.

@NXP, please feel free to correct me if anything wrong.

Thanks,
Chester

[1] https://www.nxp.com/webapp/Download?colCode=GMACSUBSYSRM -> Membership
subscription is required although it's free IIRC.