Hi Andrew,

On Fri, Nov 04, 2022 at 02:30:11PM +0100, Andrew Lunn wrote:

quoted

Here I just focus on GMAC since there are other LAN interfaces that S32 family
uses [e.g. PFE]. According to the public GMACSUBSYS ref manual rev2[1] provided
on NXP website, theoretically GMAC can run SGMII in 1000Mbps and 2500Mbps so I
assume that supporting 1000BASE-X could be achievable. I'm not sure if any S32
board variant might have SFP ports but RJ-45 [1000BASE-T] should be the major
type used on S32G-EVB and S32G-RDB2.

SGMII at 2500Mbps does not exist. Lots of people get this wrong. It
will be 2500Base-X.

Thanks for your correction.

Does the clock need to change in order to support 2500Base-X? If i

Since I'm not a hardware designer from NXP and I can't find any board that
S32G2 CPUs could integrate SFP, so I am not able to tell how the clock could
be configured while supporting 2500Base-X.

understand you correctly, Linux does not control the clocks, and so
cannot change the clocks? So that probably means you cannot actually

To be more precise, the SCMI clock protocol in ATF [ARM Trusted Firmware]
doesn't design any interface to get/set parents of a clock so that re-parenting
clocks via the SCMI clk driver [clk-scmi.c] in Linux Kernel is impossible
for this case. That means, if any board design allows run-time swap on different
phys, the dedicated clks which represent each phy-mode are required in order
to trigger clock re-parenting in ATF since different phy connections would
need different clock sources.

support 2500Base-X? Once you have Linux actually controlling the
hardware, you can then make use of an SFP or a copper PHY which
supports 2.5G. The PHY will swap its host side between SGMII and
2500Base-X depending on what the line side negotiates, 1000Base-T or
2500Base-T. The MAC driver then needs to change its configuration to
suite.

	Andrew