RE: [PATCH net-next v4 RESEND] stmmac: tegra: Add MGBE support

Hi Vladimir,

-----Original Message-----
From: Vladimir Oltean <olteanv@gmail.com>
Sent: 22 November 2022 06:56 PM
To: Bhadram Varka <redacted>
Cc: Florian Fainelli <f.fainelli@gmail.com>; Thierry Reding
[off-list ref]; David S . Miller [off-list ref]; Eric
Dumazet [off-list ref]; Jakub Kicinski [off-list ref]; Paolo
Abeni [off-list ref]; Russell King [off-list ref]; Andrew
Lunn [off-list ref]; Revanth Kumar Uppala [off-list ref];
Jonathan Hunter [off-list ref]; linux-tegra@vger.kernel.org;
netdev@vger.kernel.org
Subject: Re: [PATCH net-next v4 RESEND] stmmac: tegra: Add MGBE support

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On Tue, Nov 22, 2022 at 07:05:22AM +0000, Bhadram Varka wrote:

quoted

Reset values of XPCS IP take care of configuring the IP in 10G mode.
No need for extra register programming is required from the driver
side. The only status that the driver expects from XPCS IP is RLU to
be up which will be done by serdes_up in recent posted changes. Please
let me know if any other queries on recent changes [0]

Thank You!

[0]:
https://patchwork.ozlabs.org/project/linux-tegra/patch/20221118075744.
49442-2-ruppala@nvidia.com/

What about link status reporting, if the XPCS is connected to an SFP cage?

What I'm trying to get at is that maybe it would be useful to consider the pcs-
xpcs.c phylink pcs driver, even if your XPCS IP is memory mapped, that is not a
problem. Using mdiobus_register(), you can create your own "MDIO"
controller with custom bus read() and write() operations which translate C45
accesses as seen by the xpcs driver into proper MMIO accesses at the right
address.

Except UPHY lane bring up through XPCS IP wrapper, nothing extra done from driver.
I think serdes_up/down function pointers gave the feasibility to do the same.

If I understand the hardware model right, the XPCS MDIO bus could be
exported by a common, top-level SERDES driver. In addition to the XPCS MDIO
bus, it would also model the lanes as generic PHY devices, on which you could
call phy_set_mode_ext(serdes, PHY_MODE_ETHERNET, phy_mode), and
phy_power_on()/phy_power_off().

There is no MDIO bus in XPCS IP.

Can your SERDES lanes also operate in PCIe mode? If yes, how is the selection
between PCIe and Ethernet/XPCS done?

No. It only operates in XFI.

Please let me know if there are any comments.

Thanks!