On 20.01.2022 19:01:55, Marek Behún wrote:

On Thu, 20 Jan 2022 09:49:14 +0100
Marc Kleine-Budde [off-list ref] wrote:

quoted

On 19.01.2022 14:11:17, Marek Behún wrote:

quoted

Common PHYs and network PCSes often have the possibility to specify
peak-to-peak voltage on the differential pair - the default voltage
sometimes needs to be changed for a particular board.

Add properties `tx-p2p-microvolt` and `tx-p2p-microvolt-names` for this
purpose. The second property is needed to specify the mode for the
corresponding voltage in the `tx-p2p-microvolt` property, if the voltage
is to be used only for speficic mode. More voltage-mode pairs can be
specified.

Example usage with only one voltage (it will be used for all supported
PHY modes, the `tx-p2p-microvolt-names` property is not needed in this
case):

  tx-p2p-microvolt = <915000>;

Example usage with voltages for multiple modes:

  tx-p2p-microvolt = <915000>, <1100000>, <1200000>;
  tx-p2p-microvolt-names = "2500base-x", "usb", "pcie";

Add these properties into a separate file phy/transmit-amplitude.yaml,
which should be referenced by any binding that uses it.  

If I understand your use-case correctly, you need different voltage p2p
levels in the connection between the Ethernet MAC and the Ethernet
switch or Ethernet-PHY?

This is a SerDes differential pair amplitude. So yes to your question,
if the MII interface uses differential pair, like sgmii, 10gbase-r, ...

quoted

Some of the two wire Ethernet standards (10base-T1S, 10base-T1L,
100base-T1, 1000base-T1) defines several p2p voltage levels on the wire,
i.e. between the PHYs. Alexandru has posed a series where you can
specify the between-PHY voltage levels:

| https://lore.kernel.org/all/20211210110509.20970-8-alexandru.tachici@analog.com/ (local)

Copper ethernet is something different, so no conflict

quoted

Can we make clear that your binding specifies the voltage level on the
MII interface, in contrast Alexandru's binding?

The binding explicitly says "common PHY", not ethernet PHY. I don't
thing there will be any confusion. It can also be specified for USB3+
differential pairs, or PCIe differential pairs, or DisplayPort
differential pairs...

Thanks for the clarification.

regards,
Marc

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