It is being observed some time the Ethernet interface
will not send / recive any packet after reboot.
Earlier I had submitted Ethernet reset ID patch
but it did not resolve it issue much, Adding new
reset controller of the Ethernet PHY for Amlogic SoC
could help resolve the issue.
Thanks
-Anand
Anand Moon (3):
arm64: dts: amlogic: add missing ethernet reset ID
ARM: dts: meson: Use new reset id for reset controller
net: stmmac: dwmac-meson8b: Add reset controller for ethernet phy
arch/arm/boot/dts/meson8b.dtsi | 2 +-
arch/arm/boot/dts/meson8m2.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 2 ++
.../boot/dts/amlogic/meson-g12-common.dtsi | 2 ++
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 3 +++
.../ethernet/stmicro/stmmac/dwmac-meson8b.c | 20 +++++++++++++++++++
6 files changed, 29 insertions(+), 2 deletions(-)
--
2.32.0
@@ -384,6 +386,17 @@ static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)meson8b_dwmac_mask_bits(dwmac,PRG_ETH0,PRG_ETH0_TX_AND_PHY_REF_CLK,PRG_ETH0_TX_AND_PHY_REF_CLK);+/* Make sure the Ethernet PHY is properly reseted, as U-Boot may leave+*itatdeassertedstate,andthusitmayfailtoresetEMAC.+*+*ThisassumesthedriverhasexclusiveaccesstotheEPHYreset.+*/+ret=reset_control_reset(dwmac->eth_reset);+if(ret){+dev_err(dwmac->dev,"Cannot reset internal PHY\n");+returnret;+}+return0;}
@@ -465,6 +478,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev)gotoerr_remove_config_dt;}+dwmac->eth_reset=devm_reset_control_get_exclusive(dwmac->dev,"ethreset");+if(IS_ERR_OR_NULL(dwmac->eth_reset)){+dev_err(dwmac->dev,"Failed to get Ethernet reset\n");+ret=PTR_ERR(dwmac->eth_reset);+gotoerr_remove_config_dt;+}+ret=meson8b_init_rgmii_delays(dwmac);if(ret)gotoerr_remove_config_dt;
From: Andrew Lunn <andrew@lunn.ch> Date: 2021-07-29 20:21:10
quoted hunk
@@ -465,6 +478,13 @@ static int meson8b_dwmac_probe(struct platform_device *pdev) goto err_remove_config_dt; }+ dwmac->eth_reset = devm_reset_control_get_exclusive(dwmac->dev, "ethreset");+ if (IS_ERR_OR_NULL(dwmac->eth_reset)) {+ dev_err(dwmac->dev, "Failed to get Ethernet reset\n");+ ret = PTR_ERR(dwmac->eth_reset);+ goto err_remove_config_dt;+ }+
Hi Anand
Since this is a new property, you need to handle it not being in the
DT blob. You probably need to use
devm_reset_control_get_optinal_exclusive()
Andrew
This is missing binding documentation. Also, is this reset name taken
from the documentation? Otherwise, it would probably be better to call
it "phy" for a PHY reset.
regards
Philipp
This looks like an incompatible change. Is the "stmmaceth" reset not
used? It is documented as "MAC reset signal" in [1]. So a PHY reset
should be separate from this.
[1] Documentation/devicetree/bindings/net/snps,dwmac.yaml
regards
Philipp
This looks like an incompatible change. Is the "stmmaceth" reset not
used? It is documented as "MAC reset signal" in [1]. So a PHY reset
should be separate from this.
[1] Documentation/devicetree/bindings/net/snps,dwmac.yaml
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: 2021-08-03 20:41:24
Hi Anand,
On Thu, Jul 29, 2021 at 10:11 PM Anand Moon [off-list ref] wrote:
It is being observed some time the Ethernet interface
will not send / recive any packet after reboot.
Earlier I had submitted Ethernet reset ID patch
but it did not resolve it issue much, Adding new
reset controller of the Ethernet PHY for Amlogic SoC
could help resolve the issue.
From: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Date: 2021-08-03 20:45:29
Hi Anand,
On Thu, Jul 29, 2021 at 10:11 PM Anand Moon [off-list ref] wrote:
Add reset controller for Ethernet phy reset on every boot for
Amlogic SoC.
I think this description does not match what's going on inside the SoC:
- for all SoCs earlier than GXL the PHY is external so the reset for
the PHY is a GPIO
- the reset line you are passing in the .dts belongs to the Ethernet
controller on SoCs earlier than GXL
- I *believe* that the rset line which you're passing in the .dts
belongs to the Ethernet controller AND the built-in MDIO mux on GXL
and newer, see also [0]
- from how the PRG_ETH registers work I doubt that these are connected
to a reset line (as they're managing mostly delays and protocol - so I
don't see what would be reset). This is speculation though.
Best regards,
Martin
[0] https://lore.kernel.org/linux-amlogic/553e127c-9839-d15b-d435-c01f18c7be48@gmail.com/