[PATCH 3/6] dt-bindings: clk: r9a07g044-cpg: Add entry for P0_DIV2 core clock
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: 2021-07-15 18:21:56
Also in:
linux-can, linux-clk, linux-devicetree, linux-renesas-soc, lkml
Subsystem:
common clk framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Add P0_DIV2 core clock required for CANFD module. CANFD core clock is sourced from P0_DIV2 referenced from HW manual Rev.0.50. Also add R9A07G044_LAST_CORE_CLK entry to avoid changes in r9a07g044-cpg.c file. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> --- include/dt-bindings/clock/r9a07g044-cpg.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/r9a07g044-cpg.h b/include/dt-bindings/clock/r9a07g044-cpg.h
index 0728ad07ff7a..2fd20db0b2f4 100644
--- a/include/dt-bindings/clock/r9a07g044-cpg.h
+++ b/include/dt-bindings/clock/r9a07g044-cpg.h@@ -30,6 +30,8 @@ #define R9A07G044_CLK_P2 19 #define R9A07G044_CLK_AT 20 #define R9A07G044_OSCCLK 21 +#define R9A07G044_CLK_P0_DIV2 22 +#define R9A07G044_LAST_CORE_CLK 23 /* R9A07G044 Module Clocks */ #define R9A07G044_CA55_SCLK 0
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2.17.1