Re: [PATCH v7 net-next 04/15] net: mvpp2: add PPv23 version definition

From: Stefan Chulski <redacted>

This patch add PPv23 version definition.
PPv23 is new packet processor in CP115.
Everything that supported by PPv22, also supported by PPv23.
No functional changes in this stage.

Signed-off-by: Stefan Chulski <redacted>
---
 drivers/net/ethernet/marvell/mvpp2/mvpp2.h      | 24 ++++++++++++--------
 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 17 +++++++++-----
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
index aec9179..89b3ede 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2.h

@@ -60,6 +60,9 @@
 /* Top Registers */
 #define MVPP2_MH_REG(port)                     (0x5040 + 4 * (port))
 #define MVPP2_DSA_EXTENDED                     BIT(5)
+#define MVPP2_VER_ID_REG                       0x50b0
+#define MVPP2_VER_PP22                         0x10
+#define MVPP2_VER_PP23                         0x11

 /* Parser Registers */
 #define MVPP2_PRS_INIT_LOOKUP_REG              0x1000

@@ -469,7 +472,7 @@
 #define     MVPP22_GMAC_INT_SUM_MASK_LINK_STAT BIT(1)
 #define            MVPP22_GMAC_INT_SUM_MASK_PTP        BIT(2)

-/* Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
+/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
  * relative to port->base.
  */
 #define MVPP22_XLG_CTRL0_REG                   0x100

@@ -506,7 +509,7 @@
 #define     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC BIT(12)
 #define     MVPP22_XLG_CTRL4_EN_IDLE_CHECK     BIT(14)

-/* SMI registers. PPv2.2 only, relative to priv->iface_base. */
+/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
 #define MVPP22_SMI_MISC_CFG_REG                        0x1204
 #define     MVPP22_SMI_POLLING_EN              BIT(10)

@@ -582,7 +585,7 @@
 #define MVPP2_QUEUE_NEXT_DESC(q, index) \
        (((index) < (q)->last_desc) ? ((index) + 1) : 0)

-/* XPCS registers. PPv2.2 only */
+/* XPCS registers.PPv2.2 and PPv2.3 */
 #define MVPP22_MPCS_BASE(port)                 (0x7000 + (port) * 0x1000)
 #define MVPP22_MPCS_CTRL                       0x14
 #define     MVPP22_MPCS_CTRL_FWD_ERR_CONN      BIT(10)

@@ -593,7 +596,7 @@
 #define     MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
 #define     MVPP22_MPCS_CLK_RESET_DIV_SET      BIT(11)

-/* XPCS registers. PPv2.2 only */
+/* XPCS registers. PPv2.2 and PPv2.3 */
 #define MVPP22_XPCS_BASE(port)                 (0x7400 + (port) * 0x1000)
 #define MVPP22_XPCS_CFG0                       0x0
 #define     MVPP22_XPCS_CFG0_RESET_DIS         BIT(0)

@@ -930,15 +933,16 @@ struct mvpp2 {
        void __iomem *iface_base;
        void __iomem *cm3_base;

-       /* On PPv2.2, each "software thread" can access the base
+       /* On PPv2.2 and PPv2.3, each "software thread" can access the base
         * register through a separate address space, each 64 KB apart
         * from each other. Typically, such address spaces will be
         * used per CPU.
         */
        void __iomem *swth_base[MVPP2_MAX_THREADS];

-       /* On PPv2.2, some port control registers are located into the system
-        * controller space. These registers are accessible through a regmap.
+       /* On PPv2.2 and PPv2.3, some port control registers are located into
+        * the system controller space. These registers are accessible
+        * through a regmap.
         */
        struct regmap *sysctrl_base;

@@ -980,7 +984,7 @@ struct mvpp2 {
        u32 tclk;

        /* HW version */
-       enum { MVPP21, MVPP22 } hw_version;
+       enum { MVPP21, MVPP22, MVPP23 } hw_version;

        /* Maximum number of RXQs per port */
        unsigned int max_port_rxqs;

@@ -1227,7 +1231,7 @@ struct mvpp21_rx_desc {
        __le32 reserved8;
 };

-/* HW TX descriptor for PPv2.2 */
+/* HW TX descriptor for PPv2.2 and PPv2.3 */
 struct mvpp22_tx_desc {
        __le32 command;
        u8  packet_offset;

@@ -1239,7 +1243,7 @@ struct mvpp22_tx_desc {
        __le64 buf_cookie_misc;
 };

-/* HW RX descriptor for PPv2.2 */
+/* HW RX descriptor for PPv2.2 and PPv2.3 */
 struct mvpp22_rx_desc {
        __le32 status;
        __le16 reserved1;

diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
index 307f9fd..11c56d2 100644
--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

@@ -385,7 +385,7 @@ static int mvpp2_bm_pool_create(struct device *dev, struct mvpp2 *priv,
        if (!IS_ALIGNED(size, 16))
                return -EINVAL;

-       /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 needs 16
+       /* PPv2.1 needs 8 bytes per buffer pointer, PPv2.2 and PPv2.3 needs 16

         * bytes per buffer pointer
         */
        if (priv->hw_version == MVPP21)

@@ -1173,7 +1173,7 @@ static void mvpp2_interrupts_unmask(void *arg)
        u32 val;
        int i;

-       if (port->priv->hw_version != MVPP22)
+       if (port->priv->hw_version == MVPP21)
                return;