RE: [PATCH net-next 0/2] Fix 10G PHY interface types

-----Original Message-----
From: Andrew Lunn <andrew@lunn.ch>
Sent: Friday, January 3, 2020 6:48 PM
To: Madalin Bucur (OSS) <redacted>
Cc: Russell King - ARM Linux admin <linux@armlinux.org.uk>; Florian
Fainelli [off-list ref]; Heiner Kallweit [off-list ref];
David S. Miller [off-list ref]; Jonathan Corbet [off-list ref];
Kishon Vijay Abraham I [off-list ref]; linux-doc@vger.kernel.org;
netdev@vger.kernel.org
Subject: Re: [PATCH net-next 0/2] Fix 10G PHY interface types

quoted

And here is a LS1046A SoC document that describes XFI and 10GBASE_KR:

https://www.mouser.com/pdfdocs/LS1046A.pdf

You need to register, unfortunately, but the information is in the reference
manual (18.3 MB of download):

https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1046a-and-1026a-multicore-communications-processors:LS1046A?tab=Documentation_Tab

You can find there also an application note on the backplane ethernet
support on this device, with a description of the current solution, describing
the SoC internal PCS (manageable through an MDIO bus) as a PHY to be able
to use the PHYlib infrastructure to control it. The code is still under
refinement, not upstream yet, but it's available and in use by customers.

I don't see any register descriptions here. So you failed to answer my
question. What do you actually need to configure? What needs to go
into DT?

You keep avoiding the questions Russell and I pose, which is not
helping your argument. We need details, not hand waiving.

	Andrew

Answers are there, spreading the conversation on multiple threads and
removing history is not helping.

Madalin