Re: [PATCH v4 06/17] octeontx2-pf: Receive packet handling support
From: Jakub Kicinski <kuba@kernel.org>
Date: 2020-01-21 16:33:26
On Tue, 21 Jan 2020 18:51:40 +0530, sunil.kovvuri@gmail.com wrote:
static int otx2_rx_napi_handler(struct otx2_nic *pfvf, struct napi_struct *napi, struct otx2_cq_queue *cq, int budget)
quoted hunk ↗ jump to hunk
+ int processed_cqe = 0; + s64 bufptr; + + /* Make sure HW writes to CQ are done */ + dma_rmb();
What is this memory barrier between? Usually dma_rmb() barrier is placed between accesses to the part of the descriptor which tells us device is done and the rest of descriptor accesses.
quoted hunk ↗ jump to hunk
+ while (likely(processed_cqe < budget)) { + cqe = (struct nix_cqe_rx_s *)CQE_ADDR(cq, cq->cq_head); + if (cqe->hdr.cqe_type == NIX_XQE_TYPE_INVALID || + !cqe->sg.subdc) { + if (!processed_cqe) + return 0; + break; + } + cq->cq_head++; + cq->cq_head &= (cq->cqe_cnt - 1); + + otx2_rcv_pkt_handler(pfvf, napi, cq, cqe); + + cqe->hdr.cqe_type = NIX_XQE_TYPE_INVALID; + cqe->sg.subdc = NIX_SUBDC_NOP; + processed_cqe++; + }
quoted hunk ↗ jump to hunk
+void otx2_cleanup_rx_cqes(struct otx2_nic *pfvf, struct otx2_cq_queue *cq) +{ + struct nix_cqe_rx_s *cqe; + int processed_cqe = 0; + u64 iova, pa; + + /* Make sure HW writes to CQ are done */ + dma_rmb();
ditto
quoted hunk ↗ jump to hunk
+ while ((cqe = (struct nix_cqe_rx_s *)otx2_get_next_cqe(cq))) { + if (!cqe->sg.subdc) + continue; + iova = cqe->sg.seg_addr - OTX2_HEAD_ROOM; + pa = otx2_iova_to_phys(pfvf->iommu_domain, iova); + otx2_dma_unmap_page(pfvf, iova, pfvf->rbsize, DMA_FROM_DEVICE); + put_page(virt_to_page(phys_to_virt(pa))); + processed_cqe++; + } + + /* Free CQEs to HW */ + otx2_write64(pfvf, NIX_LF_CQ_OP_DOOR, + ((u64)cq->cq_idx << 32) | processed_cqe); +}