[PATCH 5/6] net/wan/fsl_ucc_hdlc: GUMR for non tsa mode
From: David Gounaris <hidden>
Date: 2018-08-28 11:15:41
Also in:
linuxppc-dev
Subsystem:
freescale quicc engine ucc hdlc driver, networking drivers, the rest · Maintainers:
Zhao Qiang, Andrew Lunn, "David S. Miller", Eric Dumazet, Jakub Kicinski, Paolo Abeni, Linus Torvalds
The following bits in the GUMR is changed for non tsa mode: CDS, CTSP and CTSS are set to zero. When set, there is no tx interrupts from the controller. Signed-off-by: David Gounaris <redacted> --- drivers/net/wan/fsl_ucc_hdlc.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index 54e2b2143e36..e6154a6547e6 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c@@ -97,6 +97,13 @@ static int uhdlc_init(struct ucc_hdlc_private *priv) if (priv->tsa) { uf_info->tsa = 1; uf_info->ctsp = 1; + uf_info->cds = 1; + uf_info->ctss = 1; + } + else { + uf_info->cds = 0; + uf_info->ctsp = 0; + uf_info->ctss = 0; } /* This sets HPM register in CMXUCR register which configures a
--
2.13.6