Thread (8 messages) 8 messages, 3 authors, 2017-08-19

RE: [PATCH net v2 2/2] net: ixgbe: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag

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From: Tantilov, Emil S <hidden>
Date: 2017-08-18 05:04:09
Also in: intel-wired-lan, lkml, sparclinux

-----Original Message-----
From: Ding Tianhong [mailto:<redacted>]
Sent: Thursday, August 17, 2017 5:39 PM
To: Tantilov, Emil S <redacted>; davem@davemloft.net;
Kirsher, Jeffrey T [off-list ref]; keescook@chromium.org;
linux-kernel@vger.kernel.org; sparclinux@vger.kernel.org; intel-wired-
lan@lists.osuosl.org; alexander.duyck@gmail.com; netdev@vger.kernel.org;
linuxarm@huawei.com
Subject: Re: [PATCH net v2 2/2] net: ixgbe: Use new
PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag



On 2017/8/17 22:17, Tantilov, Emil S wrote:
quoted
quoted
	ret_val = ixgbe_start_hw_generic(hw);

-#ifndef CONFIG_SPARC
-	/* Disable relaxed ordering */
-	for (i = 0; ((i < hw->mac.max_tx_queues) &&
-	     (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
-		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
-		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
-		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
-	}
+	if (!pcie_relaxed_ordering_enabled(adapter->pdev)) {
As Alex mentioned there is no need for this check in any form.

The HW defaults to Relaxed Ordering enabled unless it is disabled in
the PCIe Device Control Register. So the above logic is already done by
HW.
quoted
All you have to do is strip the code disabling relaxed ordering.
Hi Tantilov:

I misunderstood Alex's suggestion, But I still couldn't find the logic
where
the HW disable the Relaxed Ordering when the PCIe Device Control Register
disable it, can you point it out?
If you look at the datasheet (82599) - the description of CTRL_EXT.RO_DIS (bit 17, 0b):

Relaxed Ordering Disable. When set to 1b, the device does not request any relaxed
ordering transactions. When this bit is cleared and the Enable Relaxed Ordering bit in
the Device Control register is set, the device requests relaxed ordering transactions per queues as configured in the DCA_RXCTRL[n] and DCA_TXCTRL[n] registers.

So if you remove the code that clears the bits in DCA_T/RXCTRL relaxed ordering should
be enabled by HW when the bus allows it.

Thanks,
Emil
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