Re: [PATCH 8/9] MIPS: xilfpga: Add DT node for AXI emaclite

Hi,

On 08/15/2016 04:17 PM, Jason Cooper wrote:

Hi Zubair,

On Mon, Aug 15, 2016 at 02:55:34PM +0100, Zubair Lutfullah Kakakhel wrote:

quoted

The xilfpga platform has a Xilinx AXI emaclite block.

Add the DT node to use it.

Signed-off-by: Zubair Lutfullah Kakakhel <redacted>
---
 arch/mips/boot/dts/xilfpga/nexys4ddr.dts | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)

diff --git a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
index 3658e21..58bc62f 100644
--- a/arch/mips/boot/dts/xilfpga/nexys4ddr.dts
+++ b/arch/mips/boot/dts/xilfpga/nexys4ddr.dts

@@ -42,6 +42,33 @@
 		xlnx,tri-default = <0xffffffff>;
 	} ;

+	axi_ethernetlite: ethernet@10e00000 {
+		compatible = "xlnx,xps-ethernetlite-3.00.a";

This one also isn't documented.

These are sort of documented. Although checkpatch probably won't find them.

Xilinx IP blocks follow a generic DT style as documented here.

http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/xilinx.txt

quoted

+		device_type = "network";
+		interrupt-parent = <&axi_intc>;
+		interrupts = <1>;
+		local-mac-address = [08 86 4C 0D F7 09];

I'm pretty sure you don't want this in the mainline dts file.

Oops. Sorry. I'll remove it.

Thanks
ZubairLK

thx,

Jason.

quoted

+		phy-handle = <&phy0>;
+		reg = <0x10e00000 0x10000>;
+		xlnx,duplex = <0x1>;
+		xlnx,include-global-buffers = <0x1>;
+		xlnx,include-internal-loopback = <0x0>;
+		xlnx,include-mdio = <0x1>;
+		xlnx,instance = "axi_ethernetlite_inst";
+		xlnx,rx-ping-pong = <0x1>;
+		xlnx,s-axi-id-width = <0x1>;
+		xlnx,tx-ping-pong = <0x1>;
+		xlnx,use-internal = <0x0>;
+		mdio {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			phy0: phy@1 {
+				device_type = "ethernet-phy";
+				reg = <1>;
+			};
+		};
+	};
+
 	axi_uart16550: serial@10400000 {
 		compatible = "ns16550a";
 		reg = <0x10400000 0x10000>;
--
1.9.1