Hi David, Thomas,

On Thu, 31 Mar 2016 16:47:10 -0400 David Miller  wrote:

From: Thomas Petazzoni <redacted>
Date: Thu, 31 Mar 2016 22:37:35 +0200

quoted

Hello,

On Thu, 31 Mar 2016 15:15:47 -0400 (EDT), David Miller wrote:  

quoted

From: Jisheng Zhang <redacted>
Date: Wed, 30 Mar 2016 19:55:21 +0800
  

quoted

The mvneta is also used in some Marvell berlin family SoCs which may
have 64bytes cacheline size. Replace the MVNETA_CPU_D_CACHE_LINE_SIZE
usage with L1_CACHE_BYTES.

And since dma_alloc_coherent() is always cacheline size aligned, so
remove the align checks.

Signed-off-by: Jisheng Zhang <redacted>  

Applied.  

A new version of the patch was sent, which more rightfully uses
cache_line_size(), see:

 "[PATCH v2] net: mvneta: replace MVNETA_CPU_D_CACHE_LINE_SIZE with cache_line_size"  

Sorry about that.

Send me a realtive fixup patch if you like.

Sorry about inconvenience, I'll send out fixup patch.

Thanks,
Jisheng