Re: [PATCH 3/7] net: phy: spi_ks8995: add register initialization

At the moment I use this driver with a KSZ8795CLX, port 5 directly
connected to a MACB/GEM of a Zynq SOC, with the need to enable the
RGMII internal clock delay (register 0x56,  bit 4), otherwise the
the Zynq cannot talk to the switch on its RGMII interface

Hi Helmut

This is possible with DSA.
Documentation/devicetree/bindings/net/dsa/dsa.txt says you can include
a phy-mode setting. phy-mode is defined in
Documentation/devicetree/bindings/net/ethernet.txt and includes
"rgmii-id", "rgmii-rxid", "rgmii-txid" which control these delays.

    Andrew