From: Helmut Buchsbaum <hidden> Date: 2016-02-07 22:39:55
This patch series refactors the spi-ks8995 driver to finally add support
for the MICREL KSZ8795CLX. Additionally support for setting initial
register values as well as controlling a GPIO line for resetting the
switch is added.
Helmut Buchsbaum (7):
net: phy: spi_ks8995: introduce spi_device_id table
net: phy: spi_ks8995: add chip verification and determine chip
revision
net: phy: spi_ks8995: add ability to configure register initialization
net: phy: spi_ks8995: add support for resetting switch using GPIO
net: phy: spi_ks8995: generalize creation of SPI commands
net: phy: spi_ks8995: add support for MICREL KSZ8795CLX 5-Port managed
switch
dt-bindings: net: ks8995: add documentation for MICREL ks8995 driver
.../devicetree/bindings/net/micrel-ks8995.txt | 27 ++
drivers/net/phy/spi_ks8995.c | 407 +++++++++++++++++----
2 files changed, 371 insertions(+), 63 deletions(-)
create mode 100644 Documentation/devicetree/bindings/net/micrel-ks8995.txt
--
2.1.4
From: Helmut Buchsbaum <hidden> Date: 2016-02-07 22:39:57
Since the chip variant is now determined by spi_device_id, verify
family and chip id and determine the revision id.
Conflicts:
drivers/net/phy/spi_ks8995.c
Signed-off-by: Helmut Buchsbaum <redacted>
---
drivers/net/phy/spi_ks8995.c | 118 +++++++++++++++++++++++++++++--------------
1 file changed, 80 insertions(+), 38 deletions(-)
@@ -263,6 +272,73 @@ static ssize_t ks8995_registers_write(struct file *filp, struct kobject *kobj,returnks8995_write(ks8995,buf,off,count);}+/* ks8995_get_revision - get chip revision+*@ks:pointertoswitchinstance+*+*Verifychipfamilyandidandgetchiprevision.+*/+staticintks8995_get_revision(structks8995_switch*ks)+{+interr;+u8id0,id1,ksz8864_id;++/* read family id */+err=ks8995_read_reg(ks,KS8995_REG_ID0,&id0);+if(err){+err=-EIO;+gotoerr_out;+}++/* verify family id */+if(id0!=ks->chip->family_id){+dev_err(&ks->spi->dev,"chip family id mismatch: expected 0x%02x but 0x%02x read\n",+ks->chip->family_id,id0);+err=-ENODEV;+gotoerr_out;+}++switch(ks->chip->family_id){+caseFAMILY_KS8995:+/* try reading chip id at CHIP ID1 */+err=ks8995_read_reg(ks,KS8995_REG_ID1,&id1);+if(err){+err=-EIO;+gotoerr_out;+}++/* verify chip id */+if((get_chip_id(id1)==CHIPID_M)&&+(get_chip_id(id1)==ks->chip->chip_id)){+/* KS8995MA */+ks->revision_id=get_chip_rev(id1);+}elseif(get_chip_id(id1)!=CHIPID_M){+/* KSZ8864RMN */+err=ks8995_read_reg(ks,KS8995_REG_ID1,&ksz8864_id);+if(err){+err=-EIO;+gotoerr_out;+}++if((ksz8864_id&0x80)&&+(ks->chip->chip_id==KSZ8864_CHIP_ID)){+ks->revision_id=get_chip_rev(id1);+}++}else{+dev_err(&ks->spi->dev,"unsupported chip id for KS8995 family: 0x%02x\n",+id1);+err=-ENODEV;+}+break;+default:+dev_err(&ks->spi->dev,"unsupported family id: 0x%02x\n",id0);+err=-ENODEV;+break;+}+err_out:+returnerr;+}+staticconststructbin_attributeks8995_registers_attr={.attr={.name="registers",
@@ -278,7 +354,6 @@ static int ks8995_probe(struct spi_device *spi){structks8995_switch*ks;structks8995_pdata*pdata;-u8ids[2];interr;intvariant=spi_get_device_id(spi)->driver_data;
@@ -309,39 +384,12 @@ static int ks8995_probe(struct spi_device *spi)returnerr;}-err=ks8995_read(ks,ids,KS8995_REG_ID0,sizeof(ids));-if(err<0){-dev_err(&spi->dev,"unable to read id registers, err=%d\n",-err);+err=ks8995_get_revision(ks);+if(err)returnerr;-}--switch(ids[0]){-caseFAMILY_KS8995:-break;-default:-dev_err(&spi->dev,"unknown family id:%02x\n",ids[0]);-return-ENODEV;-}ks->regs_attr.size=ks->chip->regs_size;memcpy(&ks->regs_attr,&ks8995_registers_attr,sizeof(ks->regs_attr));-if(get_chip_id(ids[1])!=CHIPID_M){-u8val;--/* Check if this is a KSZ8864RMN */-err=ks8995_read(ks,&val,KSZ8864_REG_ID1,sizeof(val));-if(err<0){-dev_err(&spi->dev,-"unable to read chip id register, err=%d\n",-err);-returnerr;-}-if((val&0x80)==0){-dev_err(&spi->dev,"unknown chip:%02x,0\n",ids[1]);-returnerr;-}-}err=ks8995_reset(ks);if(err)
From: Helmut Buchsbaum <hidden> Date: 2016-02-07 22:39:58
Since several use cases need to setup at least some basic control
registers add the ability to configure an array containing such
register initialization values within the platform data of the switch.
Furthermore expose this capabilty to the devicetree.
Platform data now contains a pointer to an array and the array length
where each member contains the register to be initialized, the
initialization value and a register mask, since in many use cases there
is only the need to init some bits of a register, e.g. disabling unused
ports.
The devicetree notation add the property 'settings' to the SPI node of the
ks8985 driver, which is a list of triple values (register, value, mask),
e.g.:
settings = <0x4D 0x08 0x08
0x5D 0x08 0x08>;
to power down port 3 and 4 of a KSZ8864RMN.
Signed-off-by: Helmut Buchsbaum <redacted>
---
drivers/net/phy/spi_ks8995.c | 136 ++++++++++++++++++++++++++++++++++++++++---
1 file changed, 128 insertions(+), 8 deletions(-)
@@ -245,6 +292,10 @@ static int ks8995_reset(struct ks8995_switch *ks)udelay(KS8995_RESET_DELAY);+err=ks8995_register_init(ks);+if(err)+returnerr;+returnks8995_start(ks);}
@@ -339,6 +390,64 @@ err_out:returnerr;}+/* ks8995_parse_dt - setup platform data from devicetree+*@ks:pointertoswitchinstance+*+*ParsessupportedDTpropertiesandsetsupplatformdata+*accordingly.+*/+staticintks8995_parse_dt(structks8995_switch*ks)+{+const__be32*settings;+intsize,nsettings,i;+structdevice_node*np=ks->spi->dev.of_node;+structks8995_pdata*pdata=ks->pdata;++if(!np)+return0;++/* we have something like:+*settings=<0x220x800xF0>;+*^^^+*|||+*||+registerbitmask+*|+registervalue+*+registernumber+*+*formultipleregistersitis+*+*settings=<0x220x800xF00x230x010xFF>;+*/+settings=of_get_property(np,"settings",&size);+if(!settings)+return0;++if(size<sizeof(*settings)*2){+dev_err(&ks->spi->dev,"bad data for settings\n");+return-EINVAL;+}++size/=sizeof(*settings);/* Number of elements in DT array */+nsettings=size/3;/* Number of register settings */++pdata->settings=devm_kzalloc(&ks->spi->dev,+sizeof(*pdata->settings)*nsettings,GFP_KERNEL);++if(!pdata->settings)+return-ENOMEM;++for(i=0;i<nsettings;++i){+structreg_init*s=&pdata->settings[i];++s->reg=be32_to_cpup(settings+3*i);+s->val=be32_to_cpup(settings+3*i+1);+s->mask=be32_to_cpup(settings+3*i+2);+}+pdata->nsettings=nsettings;++return0;+}+staticconststructbin_attributeks8995_registers_attr={.attr={.name="registers",
From: Helmut Buchsbaum <hidden> Date: 2016-02-07 22:39:59
When using device tree it is no more possible to reset the PHY at board
level. Furthermore, doing in the driver allows to power down the switch
when the it is not used any more.
The patch introduces a new optional property "reset-gpios" denoting an
appropriate GPIO handle, e.g.:
reset-gpios = <&gpio0 46 1>
Signed-off-by: Helmut Buchsbaum <redacted>
---
drivers/net/phy/spi_ks8995.c | 23 ++++++++++++++++++++++-
1 file changed, 22 insertions(+), 1 deletion(-)
@@ -406,6 +409,8 @@ static int ks8995_parse_dt(struct ks8995_switch *ks)if(!np)return0;+pdata->reset_gpio=of_get_named_gpio(np,"reset-gpios",0);+/* we have something like:*settings=<0x220x800xF0>;*^^^
@@ -484,6 +489,8 @@ static int ks8995_probe(struct spi_device *spi)if(!ks->pdata)return-ENOMEM;+ks->pdata->reset_gpio=-1;+err=ks8995_parse_dt(ks);if(err){dev_err(&ks->spi->dev,"bad data DT data\n");
@@ -494,6 +501,18 @@ static int ks8995_probe(struct spi_device *spi)if(!ks->pdata)ks->pdata=spi->dev.platform_data;+if(ks->pdata&&gpio_is_valid(ks->pdata->reset_gpio)){+err=devm_gpio_request_one(&spi->dev,+ks->pdata->reset_gpio,+GPIOF_OUT_INIT_HIGH,+"switch-reset");+if(err){+dev_err(&spi->dev,+"failed to get reset-gpios: %d\n",err);+return-EIO;+}+}+spi_set_drvdata(spi,ks);spi->mode=SPI_MODE_0;
From: Helmut Buchsbaum <hidden> Date: 2016-02-07 22:40:00
Prepare creating SPI reads and writes for other switch families.
The KS8995 family uses the straight forward
<8bit CMD><8bit ADDR>
sequence.
To be able to support KSZ8795 family, which uses
<3bit CMD><12bit ADDR><1 bit TR>
make the SPI command creation chip variant dependent.
Signed-off-by: Helmut Buchsbaum <redacted>
---
drivers/net/phy/spi_ks8995.c | 46 +++++++++++++++++++++++++++++++++-----------
1 file changed, 35 insertions(+), 11 deletions(-)
@@ -408,6 +421,22 @@ static int ks8995_get_revision(struct ks8995_switch *ks)err=-ENODEV;}break;+caseFAMILY_KSZ8795:+/* try reading chip id at CHIP ID1 */+err=ks8995_read_reg(ks,KS8995_REG_ID1,&id1);+if(err){+err=-EIO;+gotoerr_out;+}++if(get_chip_id(id1)==ks->chip->chip_id){+ks->revision_id=get_chip_rev(id1);+}else{+dev_err(&ks->spi->dev,"unsupported chip id for KSZ8795 family: 0x%02x\n",+id1);+err=-ENODEV;+}+break;default:dev_err(&ks->spi->dev,"unsupported family id: 0x%02x\n",id0);err=-ENODEV;
@@ -0,0 +1,27 @@+Micrel KS8995 SPI controlled Ethernet Switch families++Required properties (according to spi-bus.txt):+- compatible: either "micrel,ks8995", "micrel,ksz8864" or "micrel,ksz8795"++Optional properties:+- settings: list of register initialization triples containing+ register offset, register value and register mask.+- reset-gpios : phandle of gpio that will be used to reset chip during probe++Example:++spi-master {+ ...+ ksz8795 {+ compatible = "micrel,ksz8795";++ reg = <0>;+ spi-max-frequency = <50000000>;+ settings = <+ 0x56 0x10 0x10 /* Enable Ingress RGMII-ID Mode */+ 0x3D 0x08 0x08 /* power down port 3 */+ 0x4D 0x08 0x08 /* power down port 4 */+ >;+ reset-gpios = <&gpio0 46 1>;+ };+};
Since several use cases need to setup at least some basic control
registers add the ability to configure an array containing such
register initialization values within the platform data of the switch.
Furthermore expose this capabilty to the devicetree.
Platform data now contains a pointer to an array and the array length
where each member contains the register to be initialized, the
initialization value and a register mask, since in many use cases there
is only the need to init some bits of a register, e.g. disabling unused
ports.
The devicetree notation add the property 'settings' to the SPI node of the
ks8985 driver, which is a list of triple values (register, value, mask),
e.g.:
settings = <0x4D 0x08 0x08
0x5D 0x08 0x08>;
You encode way too much in the Device Tree that should be knowledge to
the driver on how to configure the switch. This is very tempting,
because you do not dictate any use case and let people define it based
on their Device Tree source, but at the same time, this is very error
prone and does not provide what a proper device driver needs to be doing
by defining a standard and predictable behavior.
Right now this driver is a PHY driver, but it should be moved to a DSA
driver eventually such that each port is exposed as a network interface,
and you have hooks to power on/off ports based on whether a
corresponding network interface is up/down.
From: Helmut Buchsbaum <hidden> Date: 2016-02-08 08:29:01
On 02/08/2016 05:38 AM, Florian Fainelli wrote:
On 07/02/2016 14:39, Helmut Buchsbaum wrote:
quoted
Since several use cases need to setup at least some basic control
registers add the ability to configure an array containing such
register initialization values within the platform data of the switch.
Furthermore expose this capabilty to the devicetree.
Platform data now contains a pointer to an array and the array length
where each member contains the register to be initialized, the
initialization value and a register mask, since in many use cases there
is only the need to init some bits of a register, e.g. disabling unused
ports.
The devicetree notation add the property 'settings' to the SPI node of the
ks8985 driver, which is a list of triple values (register, value, mask),
e.g.:
settings = <0x4D 0x08 0x08
0x5D 0x08 0x08>;
You encode way too much in the Device Tree that should be knowledge to
the driver on how to configure the switch. This is very tempting,
because you do not dictate any use case and let people define it based
on their Device Tree source, but at the same time, this is very error
prone and does not provide what a proper device driver needs to be doing
by defining a standard and predictable behavior.
Right now this driver is a PHY driver, but it should be moved to a DSA
driver eventually such that each port is exposed as a network interface,
and you have hooks to power on/off ports based on whether a
corresponding network interface is up/down.
--
Florian
The way I built these initialization settings was inspired by the way it
is done in the pinctrl subsystem: there you also configure the pin
functions in a very hardware specific way (dependent on the underlying
pinctrl hardware). Thus this was just extending a principle we can find
in other subsystems of the kernel to this driver. Furthermore the
register interface is already exposed to the user space via sysfs,
which, in my opinion, is even more error prone then setting up the
Device Tree carefully.
Nevertheless, I can perfectly understand your point of view. This is
just what thought when I saw all registers are accessible from user space!
At the moment I use this driver with a KSZ8795CLX, port 5 directly
connected to a MACB/GEM of a Zynq SOC, with the need to enable the RGMII
internal clock delay (register 0x56, bit 4), otherwise the the Zynq
cannot talk to the switch on its RGMII interface (being able to switch
off unused ports is just a nice add-on I use). Using the sysfs
capabilities of this driver might be an alternative, but contradicts our
requirement to set up the network interfaces as fast as possible.
Furthermore stuff like IP_PNP or nfs root won't work. But maybe I should
try to move this kind of basic setup to bootloader - I'll investigate
this idea!
Since I'm not at all (yet) familiar with the DSA subsystem I wonder how
I could manage setting the clock delay bit with DSA. Would this be a
driver specific setting or can it be fulfilled within the subsystem?
Since I still want to share my work for the PHY only driver, is it ok if
I'll resend the patch series just without part 3 to get support for the
KSZ8795? Let's talk about the part 3 functionality and moving the driver
to DSA separately!
BTW, are there any additional links about DSA complementing the kernel
documentation?
Thanks for your comments,
Helmut
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-02-08 08:54:17
At the moment I use this driver with a KSZ8795CLX, port 5 directly
connected to a MACB/GEM of a Zynq SOC, with the need to enable the
RGMII internal clock delay (register 0x56, bit 4), otherwise the
the Zynq cannot talk to the switch on its RGMII interface
Hi Helmut
This is possible with DSA.
Documentation/devicetree/bindings/net/dsa/dsa.txt says you can include
a phy-mode setting. phy-mode is defined in
Documentation/devicetree/bindings/net/ethernet.txt and includes
"rgmii-id", "rgmii-rxid", "rgmii-txid" which control these delays.
Andrew
From: Andrew Lunn <andrew@lunn.ch> Date: 2016-02-08 09:22:08
On Sun, Feb 07, 2016 at 11:39:10PM +0100, Helmut Buchsbaum wrote:
When using device tree it is no more possible to reset the PHY at board
level. Furthermore, doing in the driver allows to power down the switch
when the it is not used any more.
The patch introduces a new optional property "reset-gpios" denoting an
appropriate GPIO handle, e.g.:
reset-gpios = <&gpio0 46 1>
/* we have something like:
* settings = <0x22 0x80 0xF0>;
* ^ ^ ^
@@ -484,6 +489,8 @@ static int ks8995_probe(struct spi_device *spi) if (!ks->pdata) return -ENOMEM;+ ks->pdata->reset_gpio = -1;+ err = ks8995_parse_dt(ks); if (err) { dev_err(&ks->spi->dev, "bad data DT data\n");
@@ -494,6 +501,18 @@ static int ks8995_probe(struct spi_device *spi) if (!ks->pdata) ks->pdata = spi->dev.platform_data;+ if (ks->pdata && gpio_is_valid(ks->pdata->reset_gpio)) {+ err = devm_gpio_request_one(&spi->dev,+ ks->pdata->reset_gpio,+ GPIOF_OUT_INIT_HIGH,
Hard coded HIGH. You should determine this from the flag....
DSA has the same functionality and does support the flag. You can copy
it from there.
Andrew