Re: [PATCH 0/3] x86_64, sfc: 128-bit memory-mapped I/O

On 08/21/2012 07:10 PM, Ben Hutchings wrote:

quoted

Yes, you have to make sure you properly enforce the necessary ordering
requirements manually (I think you can do that with sfence).

We did put an sfence after the writes to each register.  But some
systems only want to combine writes that cover an entire cache line, and
the writes covering a 128-bit register get broken back up into multiple
writes at the PCIe level.  And on some systems these are sent in
decreasing address order, which breaks the rules for writing to
TX_DESC_UPD.

To avoid this we'd have to put an sfence in between the writes to a
register, leaving us back where we started.

You realize the same applies to 128-bit writes, right?  Some cores
and/or systems will break them up.

	-hpa