On Wed, 06 Jun 2012 07:10:13 +0200
Eric Dumazet [off-list ref] wrote:

On Tue, 2012-05-29 at 23:25 +0900, Hiroaki SHIMODA wrote:

quoted

If I understand the code and spec correctly, TX interrupts are
generated when TXDCTL.WTHRESH descriptors have been accumulated
and write backed.

I tentatively changed the TXDCTL.WTHRESH to 1, then it seems
that latency spikes are disappear.

drivers/net/ethernet/intel/e1000e/e1000.h

@@ -181,7 +181,7 @@ struct e1000_info;
 #define E1000_TXDCTL_DMA_BURST_ENABLE                          \
        (E1000_TXDCTL_GRAN | /* set descriptor granularity */  \
         E1000_TXDCTL_COUNT_DESC |                             \
-        (5 << 16) | /* wthresh must be +1 more than desired */\
+        (1 << 16) | /* wthresh must be +1 more than desired */\
         (1 << 8)  | /* hthresh */                             \
         0x1f)       /* pthresh */

Was this patch officially submitted ?

Thanks !

Sorry for long delay. I'll post.
(I have no idea how to fix this problem as keeping TXDCTL.WTHRESH to 5)