On Mon, May 01, 2006 at 10:38:47PM +0200, Francois Romieu wrote:

quoted

-/* Minimum number of miliseconds used to toggle MDC clock during
+/* Minimum number of nanoseconds used to toggle MDC clock during
  * MII/GMII register access.
  */
-#define         IPG_PC_PHYCTRLWAIT           0x01
+#define		IPG_PC_PHYCTRLWAIT_NS		200

I would have expected a cycle of 400 ns (p.72/77 of the datasheet)
for a 2.5 MHz clock. Why is it cut by a two factor ?

200 ns high + 200 ns low = 400 ns clock period?