On Fri, Oct 29, 2004 at 06:06:52PM +0400, Evgeniy Polyakov wrote:

If we have a hardware accelerator chip, than we _already_ have improvements 
with even the worst async crypto layer, since software and hardware 
will work in parrallel.

This is not true. 

For example, if chip request setup and PCI transfer takes more than 
just using sw implementation. This is reality for AES and short 
packets.

--
Eugene