Evgeniy Polyakov told me that:

On 29 Oct 2004 08:42:18 -0400
jamal [off-list ref] wrote:

quoted

quoted

I am very curious if you see perfomance improvements over old scheme

in the case of a single crypto chip in a fast CPU.
It has been shown in the past that with a xeon in the range of 2Ghz the
context setup and the big lock (and lack of async) implied that
performance enhancement using a crypto chip was negligible.
IIRC, the only time it started showing anything useful was when a
compute intensive alg like 3DES was chewing packets >= 1000 bytes.

My suspicion is you will show it is better to use a crypto chip with
async;-> In the minimal you should show some improvement.

If we have a hardware accelerator chip, than we _already_ have improvements 
with even the worst async crypto layer, since software and hardware 
will work in parrallel.
I agree that multigigahertz box will beat my HIFN card, 
but I doubt it can beat 1gghz VIA.

I have a very preliminary driver for FastCrypt PCI board for 3DES at
http://www.logix.cz/michal/devel/fcrypt/
For now it works with some very ugly hacks in the current cryptoapi, but
I can give it a try with your acrypto and report the results.

I admit I haven't read your sources too deeply yet so excuse me a dumb
question - does acrypto replace or extend cryptoapi? Once I get it
running will it take over e.g. encryption for IPsec?

Michal Ludvig
-- 
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