Re: [PATCH v2 00/10] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs

On Wed, 08 Jul 2026 12:15:13 +0200, Paul Louvel wrote:

This series modernizes the QUICC Engine Port Interrupt Controller (QE
PIC) driver and adds the ability for QE GPIO pins to generate interrupts
through the QE PIC, completing Christophe Leroy's prior work [1].

Christophe's series was partially merged; patches 4, 6 and 7 did not
make it to mainline.

[...]

Applied, thanks!

[01/10] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler
        commit: f9cb22ee1b94a3cc5927a3cf3a6f8d01eff8e569
[02/10] dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding
        commit: 5708dd3c5a92b9199e4d12ae835b42aed55fe35d
[03/10] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema
        commit: a9fb1bd72af0bac860df82efcd92af9e6d4300b6
[04/10] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO
        commit: 33c35fcd8ac007e497f629de105aaf5f39139d1e
[05/10] soc: fsl: qe: Use generic_handle_domain_irq()
        commit: 2f30a619841dc0fee839eabc47b9d013a34dad7e
[06/10] soc: fsl: qe: Iterate over all pending interrupts in cascade handler
        commit: 8244ee2deae73c12a35616a8eed1a88531dcb36c
[07/10] soc: fsl: qe: Handle spurious interrupts
        commit: 7c1419107a55a8d89938a9d04f9c93d9074a3ea9
[08/10] soc: fsl: qe: Convert to generic IRQ chip
        commit: f585e2fac5750ead5f697a47b8612baf927f3d10
[09/10] soc: fsl: qe: Rename irq variable to parent_irq
        commit: 8cd24ff37c299f8159dee8193f171443b331c708
[10/10] soc: fsl: qe: Add support of IRQs in QE GPIO
        commit: 4a3ba9789922560a8111ffbd09f1fde2abff639a

Best regards,
-- 
Christophe Leroy (CS GROUP) [off-list ref]