[PATCH v2 07/10] soc: fsl: qe: Handle spurious interrupts
From: Paul Louvel <hidden>
Date: 2026-07-08 10:16:06
Also in:
linux-arm-kernel, linux-devicetree, linux-gpio, lkml
Subsystem:
freescale quicc engine library, freescale soc drivers, the rest · Maintainers:
Qiang Zhao, Christophe Leroy, Linus Torvalds
When no interrupt bits are set in the event register, call handle_bad_irq() to account for the spurious interrupt before exiting the cascade handler. Signed-off-by: Paul Louvel <redacted> --- drivers/soc/fsl/qe/qe_ports_ic.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c
index bc8b68e5d1a9..29f4334db5a0 100644
--- a/drivers/soc/fsl/qe/qe_ports_ic.c
+++ b/drivers/soc/fsl/qe/qe_ports_ic.c@@ -80,9 +80,15 @@ static void qepic_cascade(struct irq_desc *desc) chained_irq_enter(chip, desc); event = ioread32be(data->reg + CEPIER); + if (!event) { + handle_bad_irq(desc); + goto out; + } + for_each_set_bit(bit, &event, 32) generic_handle_domain_irq(data->host, 31 - bit); +out: chained_irq_exit(chip, desc); }
--
2.55.0