On Fri, Oct 24, 2025 at 11:09:25AM +0800, Shuai Xue wrote:

2025/10/23 18:29, Lukas Wunner:

quoted

On Mon, Oct 20, 2025 at 10:45:31PM +0800, Shuai Xue wrote:

quoted

From PCIe spec, BIT 0-2 are logged for functions supporting Advanced
Error Handling.

I am not sure if we should clear BIT 3, and also BIT 6 (Emergency Power
Reduction Detected) and in case a AER error.

AFAIUI, bits 0 to 3 are what the PCIe r7.0 sec 6.2.1 calls
"baseline capability" error reporting.  They're supported
even if AER is not supported.

Bit 6 has nothing to do with this AFAICS.

Per PCIe r7.0 section 7.5.3.5:

  **For Functions supporting Advanced Error Handling**, errors are logged
  in this register regardless of the settings of the Uncorrectable Error
  Mask register. Default value of this bit is 0b.

From this, it's clear that bits 0 to 2 are not logged unless AER is supported.

No.  It just means that if AER is supported, the Uncorrectable Error Mask
register has no bearing on whether the bits in the Device Status register
are set.  It does not mean that the bits are only set if AER is supported.

Thanks,

Lukas