On Mon, 28 Oct 2024 at 10:31, Kirill A. Shutemov [off-list ref] wrote:

On Mon, Oct 28, 2024 at 08:44:10AM -1000, Linus Torvalds wrote:

quoted

I The *hardware* presumably uses either bit 47/56 because that's the
actual hardware width of the TLB / cache matching.

It is a guess, right?

Yes, I have no idea what they actually do.

The bug makes more sense to me if the bit number depends on the active
paging mode: this bit naturally used for indexing in top level page table.
The mistake is more understandable this way.

If I were a hardware designer - which I'm obviously not - I would
*not* make the TLB lookup be based on the paging mode at all.

Only at actual TLB fill time would I care about things like 4-vs-5
level page tables (and the canonicality check would then obviously
cause the TLB fill to not happen, so you would never have a TLB entry
that could clash with the 4-vs-5 level page table model)

So I would assume that hardware that supports 5-level paging would
just unconditionally use bits 0-56, and older hardware would just use
bits 0-47. Why put extra pointless logic in what is arguably the most
critical path of the most critical piece on the CPU?

But I have zero inside knowledge, so yes, it's all a guess.

               Linus