[PATCH v2 07/23 fix] mips: update_mmu_cache() can replace __update_tlb(): fix
From: Hugh Dickins <hughd@google.com>
Date: 2023-06-09 08:10:53
Also in:
linux-arm-kernel, linux-m68k, linux-mips, linux-mm, linux-riscv, linux-s390, linux-sh, lkml, sparclinux
Subsystem:
mips, the rest · Maintainers:
Thomas Bogendoerfer, Linus Torvalds
I expect this to fix the arch/mips/mm/tlb-r4k.c:300:16: warning: variable 'pmdp' set but not used reported by the kernel test robot; but I am uncomfortable rearranging lines in this tlb_probe_hazard() area, and would be glad for review and testing by someone familiar with mips - thanks in advance! Reported-by: kernel test robot <redacted> Closes: https://lore.kernel.org/oe-kbuild-all/202306091304.cNVIspK0-lkp@intel.com/ (local) Signed-off-by: Hugh Dickins <hughd@google.com> --- arch/mips/mm/tlb-r4k.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index c96725d17cab..80fc90d8d2f1 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c@@ -293,11 +293,13 @@ void local_flush_tlb_one(unsigned long page) void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) { - unsigned long flags; +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT pgd_t *pgdp; p4d_t *p4dp; pud_t *pudp; pmd_t *pmdp; +#endif + unsigned long flags; int idx, pid; /*
@@ -316,15 +318,15 @@ void update_mmu_cache(struct vm_area_struct *vma, pid = read_c0_entryhi() & cpu_asid_mask(¤t_cpu_data); write_c0_entryhi(address | pid); } - pgdp = pgd_offset(vma->vm_mm, address); mtc0_tlbw_hazard(); tlb_probe(); tlb_probe_hazard(); + idx = read_c0_index(); +#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT + pgdp = pgd_offset(vma->vm_mm, address); p4dp = p4d_offset(pgdp, address); pudp = pud_offset(p4dp, address); pmdp = pmd_offset(pudp, address); - idx = read_c0_index(); -#ifdef CONFIG_MIPS_HUGE_TLB_SUPPORT /* this could be a huge page */ if (ptep == (pte_t *)pmdp) { unsigned long lo;
--
2.35.3