On Tue, Jun 14, 2022 at 07:53:46AM +0000, Wenhu Wang wrote:

quoted

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+
+struct mpc85xx_l2ctlr {
+     u32     ctl;            /* 0x000 - L2 control */

What is the endian of these u32 values?  You map them directly to
memory, so they must be specified some way, right?  Please make it
obvious what they are.

Surely, the values should be u32 here, modified in v2
The controller info could be found in
"QorIQ�� P2020 Integrated Processor Reference Manual"
"Chapter 6 L2 Look-Aside Cache/SRAM"
See: http://m4udit.dinauz.org/P2020RM_rev0.pdf

That's not the answer to my question :)

These are big-endian, right?  Please mark them as such and access them
properly with the correct functions.

Yes, they are big-edian.
Does it work to add comments(about order and access functions) for the structure ahead of it��
And appending like "_be", "_access_be" or "_big_endian"? (struct mpc85xx_l2ctlr_be {����};

No, not comments, these should be of the type __be32, right?

thanks,

greg k-h