-----Original Message-----
From: Andrew Murray <redacted>
Sent: 2019年8月23日 21:36
To: Xiaowei Bao <redacted>
Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
shawnguo@kernel.org; Leo Li [off-list ref]; kishon@ti.com;
lorenzo.pieralisi@arm.co; arnd@arndb.de; gregkh@linuxfoundation.org; M.h.
Lian [off-list ref]; Mingkai Hu [off-list ref]; Roy
Zang [off-list ref]; jingoohan1@gmail.com;
gustavo.pimentel@synopsys.com; linux-pci@vger.kernel.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v2 02/10] PCI: designware-ep: Add the doorbell mode of
MSI-X in EP mode

On Thu, Aug 22, 2019 at 07:22:34PM +0800, Xiaowei Bao wrote:

quoted

Add the doorbell mode of MSI-X in EP mode.

Signed-off-by: Xiaowei Bao <redacted>
---
v2:
 - Remove the macro of no used.

 drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++++++++++
 drivers/pci/controller/dwc/pcie-designware.h    | 12 ++++++++++++
 2 files changed, 26 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c

b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 3e2b740..b8388f8 100644

--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c

@@ -480,6 +480,20 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep

*ep, u8 func_no,

quoted

 	return 0;
 }

+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8

func_no,

quoted

+				       u16 interrupt_num)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	u32 msg_data;
+
+	msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
+		   (interrupt_num - 1);
+
+	dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
+
+	return 0;
+}
+
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 			      u16 interrupt_num)
 {

diff --git a/drivers/pci/controller/dwc/pcie-designware.h

b/drivers/pci/controller/dwc/pcie-designware.h
index a0fdbf7..895a9ef 100644

--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h

@@ -88,6 +88,9 @@
 #define PCIE_MISC_CONTROL_1_OFF		0x8BC
 #define PCIE_DBI_RO_WR_EN		BIT(0)

+#define PCIE_MSIX_DOORBELL		0x948
+#define PCIE_MSIX_DOORBELL_PF_SHIFT	24
+
 /*
  * iATU Unroll-specific register definitions
  * From 4.80 core version the address translation will be made by

unroll @@ -400,6 +403,8 @@ int dw_pcie_ep_raise_msi_irq(struct

dw_pcie_ep *ep, u8 func_no,

quoted

 			     u8 interrupt_num);
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
 			     u16 interrupt_num);
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8

func_no,

quoted

+				       u16 interrupt_num);
 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
#else  static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) @@
-432,6 +437,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct

dw_pcie_ep *ep, u8 func_no,

quoted

 	return 0;
 }

+static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep

*ep,

quoted

+						     u8 func_no,
+						     u16 interrupt_num)
+{
+	return 0;
+}
+

Looks OK to me.

Reviewed-by: Andrew Murray <redacted>

Thanks a lot.

quoted

 static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum
pci_barno bar)  {  }
--
2.9.5