Re: [PATCH 4/5] arm64: dts: add QorIQ LX2160A SoC support
flat view
From: Sudeep Holla <hidden>
Date: 2018-08-21 10:17:20
Also in:
linux-arm-kernel, linux-clk, linux-devicetree, linux-pm, lkml
On Mon, Aug 20, 2018 at 12:17:15PM +0530, Vabhav Sharma wrote:
quoted hunk ↗ jump to hunk
LX2160A SoC is based on Layerscape Chassis Generation 3.2 Architecture. LX2160A features an advanced 16 64-bit ARM v8 CortexA72 processor cores in 8 cluster, CCN508, GICv3,two 64-bit DDR4 memory controller, 8 I2C controllers, 3 dspi, 2 esdhc,2 USB 3.0, mmu 500, 3 SATA, 4 PL011 SBSA UARTs etc. Signed-off-by: Ramneek Mehresh <redacted> Signed-off-by: Zhang Ying-22455 <redacted> Signed-off-by: Nipun Gupta <redacted> Signed-off-by: Priyanka Jain <redacted> Signed-off-by: Yogesh Gaur <redacted> Signed-off-by: Sriram Dash <redacted> Signed-off-by: Vabhav Sharma <redacted> --- arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 572 +++++++++++++++++++++++++ 1 file changed, 572 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsidiff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi new file mode 100644 index 0000000..e35e494 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi@@ -0,0 +1,572 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree Include file for Layerscape-LX2160A family SoC. +// +// Copyright 2018 NXP + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/memreserve/ 0x80000000 0x00010000; + +/ { + compatible = "fsl,lx2160a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + // 8 clusters having 2 Cortex-A72 cores each + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + clocks = <&clockgen 1 0>; + next-level-cache = <&cluster0_l2>;
If you expect to get cache properties in sysfs entries, you need to populate them here and for each L2 cache. [...]
quoted hunk ↗ jump to hunk
+ + rstcr: syscon@1e60000 { + compatible = "syscon"; + reg = <0x0 0x1e60000 0x0 0x4>; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&rstcr>; + offset = <0x0>; + mask = <0x2>;
Is this disabled in bootloader ? With PSCI, it's preferred to use SYSTEM_RESET/OFF. EL3 f/w may need to do some housekeeping on poweroff.
quoted hunk ↗ jump to hunk
+ }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 4>, // Physical Secure PPI, active-low
The comment says active low but the value 4 indicates it's HIGH from "include/dt-bindings/interrupt-controller/irq.h"
quoted hunk ↗ jump to hunk
+ <1 14 4>, // Physical Non-Secure PPI, active-low + <1 11 4>, // Virtual PPI, active-low + <1 10 4>; // Hypervisor PPI, active-low + }; + + pmu { + compatible = "arm,armv8-pmuv3";
More specific compatible preferably "arm,cortex-a72-pmu" ? -- Regards, Sudeep