Re: [PATCH] powernv: Properly mask POWER9 DD1 PVR for different chip types

Michael Neuling [off-list ref] writes:

On Wed, 2017-06-07 at 17:24 +1000, Michael Ellerman wrote:

quoted

Michael Neuling [off-list ref] writes:
=20

quoted

Bits 48:51 in the PVR for POWER9 represent different chip types (scale
up vs out and 12 vs 24 core). Current chips have 0 here, but could be
non-zero in the future.
=20
This changes the POWER9 DD1 mask to correctly ignore these bits 48:51.
=20
Signed-off-by: Michael Neuling <redacted>
---
=C2=A0arch/powerpc/kernel/cputable.c | 4 ++--
=C2=A01 file changed, 2 insertions(+), 2 deletions(-)

=20
Presumably we should backport this?

Actually, we need to scrap this patch.

Looks like the scale up version will be marked as DD1, but it won't need =

these

workarounds. So we need it to match on the other POWER9 entry.

OK.

/giphy "dumpster fire"

cheers