Re: [PATCH] powernv: Properly mask POWER9 DD1 PVR for different chip types

On Wed, 2017-06-07 at 17:24 +1000, Michael Ellerman wrote:

Michael Neuling [off-list ref] writes:
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quoted

Bits 48:51 in the PVR for POWER9 represent different chip types (scale
up vs out and 12 vs 24 core). Current chips have 0 here, but could be
non-zero in the future.
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This changes the POWER9 DD1 mask to correctly ignore these bits 48:51.
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Signed-off-by: Michael Neuling <redacted>
---
=C2=A0arch/powerpc/kernel/cputable.c | 4 ++--
=C2=A01 file changed, 2 insertions(+), 2 deletions(-)

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Presumably we should backport this?

Actually, we need to scrap this patch.

Looks like the scale up version will be marked as DD1, but it won't need th=
ese
workarounds. So we need it to match on the other POWER9 entry.

Mikey

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cheers
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quoted

diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputa=

ble.c

quoted

index 9b3e88b1a9..89dcd94237 100644

--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c

@@ -526,8 +526,8 @@ static struct cpu_spec __initdata cpu_specs[] =3D {

=C2=A0		.machine_check_early	=3D
__machine_check_early_realmode_p8,
=C2=A0		.platform		=3D "power8",
=C2=A0	},
-	{	/* Power9 DD1*/
-		.pvr_mask		=3D 0xffffff00,
+	{	/* Power9 DD1. Bits 48:51 represent chip type so mask
these */
+		.pvr_mask		=3D 0xffff0f00,
=C2=A0		.pvr_value		=3D 0x004e0100,
=C2=A0		.cpu_name		=3D "POWER9 (raw)",
=C2=A0		.cpu_features		=3D CPU_FTRS_POWER9_DD1,
--=C2=A0
2.11.0

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