Re: [PATCH V4 7/7] cxl: Add psl9 specific code

Le 12/04/2017 à 04:11, Michael Ellerman a écrit :

Frederic Barrat [off-list ref] writes:

quoted

Le 07/04/2017 à 16:11, Christophe Lombard a écrit :

quoted

The new Coherent Accelerator Interface Architecture, level 2, for the
IBM POWER9 brings new content and features:
- POWER9 Service Layer
- Registers
- Radix mode
- Process element entry
- Dedicated-Shared Process Programming Model
- Translation Fault Handling
- CAPP
- Memory Context ID
     If a valid mm_struct is found the memory context id is used for each
     transaction associated with the process handle. The PSL uses the
     context ID to find the corresponding process element.

Signed-off-by: Christophe Lombard <redacted>
---

I'm ok with the code. However checkpatch is complaining about a
tab/space error in native.c

I already fixed it up when I applied them (and a bunch of other things).

quoted

If you have a quick respin, I also have a comment below about the
documentation.

So please send me an incremental patch to update the doco and I'll
squash it before merging the series.

cheers

Hi,

Here is a new patch which updates the documentation based
on the complet PATCH V4 7/7.
Let me know if it suits you.
Thanks


Index: capi2_linux_prepare_patch_V4/Documentation/powerpc/cxl.txt
===================================================================

--- capi2_linux_prepare_patch_V4.orig/Documentation/powerpc/cxl.txt
+++ capi2_linux_prepare_patch_V4/Documentation/powerpc/cxl.txt

@@ -62,6 +62,7 @@ Hardware overview
     POWER8 <-----> PSL Version 8 is compliant to the CAIA Version 1.0.
     POWER9 <-----> PSL Version 9 is compliant to the CAIA Version 2.0.
     This PSL Version 9 provides new features as:
+    * Interaction with the nest MMU which resides within each P9 chip.
     * Native DMA support.
     * Supports sending ASB_Notify messages for host thread wakeup.
     * Supports Atomic operations.