Re: [PATCH V3 0/7] cxl: Add support for Coherent Accelerator Interface Architecture 2.0

Le 30/03/2017 à 06:44, Andrew Donnellan a écrit :

On 29/03/17 02:14, Christophe Lombard wrote:

quoted

This series adds support for a cxl card which supports the Coherent
Accelerator Interface Architecture 2.0.

It requires IBM Power9 system and the Power Service Layer, version 9.
The PSL provides the address translation and system memory cache for
CAIA compliant Accelerators.
the PSL attaches to the IBM Processor chip through the PCIe link using
the PSL-specific “CAPI Protocol” Transaction Layer Packets.
The PSL and CAPP communicate using PowerBus packets.
When using a PCIe link the PCIe Host Bridge (PHB) decodes the CAPI
Protocol Packets from the PSL and forwards them as PowerBus data
packets. The PSL also has an optional DMA feature which allows the AFU
to send native PCIe reads and writes to the Processor.

Today Mikey reminded me that Documentation/powerpc/cxl.txt still 
exists - we probably ought to update it.

right. good point. thanks