Re: [PATCH V3 2/7] cxl: Remove unused values in bare-metal environment.
From: Andrew Donnellan <hidden>
Date: 2017-03-29 00:23:03
On 29/03/17 02:14, Christophe Lombard wrote:
The two fields pid and tid of the structure cxl_irq_info are only used in the guest environment. To avoid confusion, it's not necessary to fill the fields in the bare-metal environment. These two fields are renamed to 'reserved' to avoid undefined behavior on bare-metal. The PSL Process and Thread Identification Register (CXL_PSL_PID_TID_An) is only used when attaching a dedicated process for PSL8 only. This register goes away in CAIA2. Signed-off-by: Christophe Lombard <redacted>
Reviewed-by: Andrew Donnellan <redacted>
quoted hunk ↗ jump to hunk
--- drivers/misc/cxl/cxl.h | 13 +++++++------ drivers/misc/cxl/hcalls.c | 4 ++-- drivers/misc/cxl/native.c | 5 ----- 3 files changed, 9 insertions(+), 13 deletions(-)diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h index 79e60ec..2bbe077 100644 --- a/drivers/misc/cxl/cxl.h +++ b/drivers/misc/cxl/cxl.h@@ -895,19 +895,20 @@ int __detach_context(struct cxl_context *ctx); * plpar_hcall9() in hvCall.S * As a consequence: * - we don't need to do any endianness conversion - * - the pid and tid are an exception. They are 32-bit values returned in - * the same 64-bit register. So we do need to worry about byte ordering. + * - the pid (reserved0) and tid (reserved1) are an exception. They are + * 32-bit values returned in the same 64-bit register. So we do need + * to worry about byte ordering. */
Comment should explain that pid/tid are now reserved0/1 because we've decided not to use them at all. -- Andrew Donnellan OzLabs, ADL Canberra andrew.donnellan@au1.ibm.com IBM Australia Limited