On Tue, Jan 10, 2017 at 02:37:00PM +0530, Gautham R. Shenoy wrote:
From: "Gautham R. Shenoy" <redacted>
Currently all the low-power idle states are expected to wake up
at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
that puts the CPU to an idle state and never returns.
On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU
is expected to wake up at the next instruction of the idle
instruction.
This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
for a variant that allows resuming operation at the instruction next
to the idle-instruction.
Signed-off-by: Gautham R. Shenoy <redacted>
---
No changes from v4
Acked-by: Balbir Singh <bsingharora@gmail.com>