Re: [PATCH 2/9] drivers: base: support cpu cache information interface to userspace via sysfs

On 26/06/14 19:50, Russell King - ARM Linux wrote:

On Thu, Jun 26, 2014 at 07:41:32PM +0100, Sudeep Holla wrote:

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Hi,

On 25/06/14 23:23, Russell King - ARM Linux wrote:

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On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:

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+=09=09coherency_line_size: the minimum amount of data that gets trans=

ferred

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So, what value to do envision this taking for a CPU where the cache
line size is 32 bytes, but each cache line has two dirty bits which
allow it to only evict either the upper or lower 16 bytes depending
on which are dirty?

IIUC most of existing implementations of cacheinfo on various architectu=

res

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are representing the cache line size as coherency_line_size, in which ca=

se I

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need fix the definition in this file.

As an example, here's an extract from the SA110 TRM:

StrongARM contains a 16KByte writeback data cache. The DC has 512 lines
of 32 bytes (8 words), arranged as a 32 way set associative cache, and
uses the virtual addresses generated by the processor. A line also
contains the physical address the block was fetched from and two dirty
bits. There is a dirty bit associated with both the first and second
half of the block. When a store hits in the cache the dirty bit
associated with it is set. When a block is evicted from the cache the
dirty bits are used to decide if all, half, or none of the block will
be written back to memory using the physical address stored with the
block. The DC is always reloaded a line at a time (8 words).

Thanks for the information. It's interesting that line is referred as block
when referring to 2 dirty bits. I am not sure if this can be mapped to=20
physical_line_partition =3D 2. Thoughts ?

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BTW will there be any architectural way of finding such configuration ?

Not that I know of.

That's bad :)

Regards,
Sudeep