Hi,

On 25/06/14 23:23, Russell King - ARM Linux wrote:

On Wed, Jun 25, 2014 at 06:30:37PM +0100, Sudeep Holla wrote:

quoted

+=09=09coherency_line_size: the minimum amount of data that gets transfe=

rred

So, what value to do envision this taking for a CPU where the cache
line size is 32 bytes, but each cache line has two dirty bits which
allow it to only evict either the upper or lower 16 bytes depending
on which are dirty?

IIUC most of existing implementations of cacheinfo on various architectures
are representing the cache line size as coherency_line_size, in which case =
I
need fix the definition in this file.

BTW will there be any architectural way of finding such configuration ?

Regards,
Sudeep