On 08/01/14 20:57, Russell King - ARM Linux wrote:

On Wed, Jan 08, 2014 at 07:26:07PM +0000, Sudeep Holla wrote:

quoted

+#if __LINUX_ARM_ARCH__ < 7 /* pre ARMv7 */
+
+#define MAX_CACHE_LEVEL=09=091=09/* Only 1 level supported */
+#define CTR_CTYPE_SHIFT=09=0924
+#define CTR_CTYPE_MASK=09=09(1 << CTR_CTYPE_SHIFT)
+
+static inline unsigned int get_ctr(void)
+{
+=09unsigned int ctr;
+=09asm volatile ("mrc p15, 0, %0, c0, c0, 1" : "=3Dr" (ctr));
+=09return ctr;
+}
+
+static enum cache_type get_cache_type(int level)
+{
+=09if (level > MAX_CACHE_LEVEL)
+=09=09return CACHE_TYPE_NOCACHE;
+=09return get_ctr() & CTR_CTYPE_MASK ?
+=09=09CACHE_TYPE_SEPARATE : CACHE_TYPE_UNIFIED;

=20
So, what do we do for CPUs that don't implement the CTR?  Just return
random rubbish based on decoding the CPU Identity register as if it
were the cache type register?
=20

I assume you referring to some particular CPUs which don't implement this.
I could not find it as optional or IMPLEMENTATION defined in ARM ARM.
I might be missing to find it or there may be exceptions.
Can you please provide more information on that ?

Regards,
Sudeep