Hi All ,


On Mon, Aug 26, 2013 at 4:08 AM, David Hawkins [off-list ref] wrote:

Hi S.Saravanan,


 Root complex's would normally interrupt a device via a PCIe write

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to a register in a BAR on the end-point (or in extended configuration
space registers depending on the hardware implementation).

MPC8640 End point implements only the Type 0 header (Page 1116) . The
header implements five BARs (Page 1165).

One of those BARs typically provides access to the PowerPC memory
mapped registers (or at least a 1MB window onto those registers).
This is how your root complex can write to some form of messaging
register.

 PCIe drivers need some way to interrupt the processor, so there must

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be an option somewhere ... for example, what are the message register
interrupts intended for? See p479

http://cache.freescale.com/files/32bit/doc/ref_manual/MPC8641DRM.pdf

(Ira and myself have not used the MPC8640 so are not familiar with
its user manual).

Message registers are for interrupting the processor. A write to
them sends an interrupt to the processor.  Actually message registers

are used by the RC to enable interrupts to the processor when an EP
sends an MSI transaction to RC. In RC driver i register separately for

the msi interrupts from all three EPs.

This is pretty much what you are looking for then right?

I successfully  mapped the Programmable Interrupt Controller registers in
the EP to the PCI space . Thus now I can write the shared message interrupt
registers in the EP from the RC over PCI . But  I am facing the following
problems now  .

1) In my driver at EP, to register for this interrupt I need to know the
hardware irq number but I can't find any interrupt number assigned  by the
PIC for the messages interrupt sources(Page 451 , MPC8641DRM manual).
2) Otherwise i need to get the virtual irq number assigned by kernel
corresponding to the message interrupt . I am unable to find a method to
get this also.

In the RC side driver i get the virtual irq number after calling
pci_enable_msi() which is straightforward.
I studied the RC code which sets up shared message interrupts (Page 481,
MPC manual)  for PCI MSI interrupts . When  msi is enabled the
"arch_setup_msi_irqs()" is called leading to the fsl_setup_msi_irqs() (
http://lxr.free-electrons.com/source/arch/powerpc/sysdev/fsl_msi.c?v=3.7#L151)
. In this function the virtual irq no is obtained as below:

*virq = irq_create_mapping(msi_data->irqhost, hwirq);*

* *
In the above function the hardware irq number is same as the value
written into the  Shared Message Signaled Interrupt Index Register (Page
482) which is strange. Further these functions are called in the RC during
pci_probe at boot time or when pci_enable_msi() is called . Thus there is a
always a PCI slave device context to it. However I  require to do it in the
EP which has no pci probing nor any  pci device reference whatsoever as it
a slave. Is this approach right  ?

The end-points interrrupt the root-complex using PCIe MSI interrupts,

whereas the root-complex interrupts an end-point by writing directly
to its MSI interrupt.


 To access them in the EP from the RC  i will have to set an inbound

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window mapping the PIC register space in the EP to the PCI mem space
assigned to it . An inbound window maps a PCI address on the bus
received by the PCIe controller to a platform address. I will try that
and let u know .

Right, as I comment above, one of the BARs typically exposes the PowerPC
internal registers.


 Feel free to discuss your ideas for your PCIe driver (eg., why start

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with rionet rather than Ira's driver), either on-list, or email Ira
and myself directly

To be frank with you there was no particular reason in starting with
rionet. Maybe because our board also had SRIO interface and we are using
rionet driver successfully. I had looked at Ira's driver later. I will
study that also and try   to come back with a skeleton for my driver.

Its always a good idea to discuss different options, and to stub out
drivers or create minimal (but functional) drivers. That way you'll
be able to see how similar your new driver is to other drivers, and
you'll quickly discover if there is a hardware feature in the
existing driver that you cannot emulate (eg., some SRIO feature
used by the rionet driver).

Right now I am trying a very primitive driver just to check the feasibility
of bi-directional communication between the RC and the EP. Once this is
established  I will be in a better position to get inputs on making it a
more effective one.

 One further note. You might want to look at rproc/rpmsg and their virtio

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driver support. That seems to be where the Linux world is moving for
inter-processor communications. See for example the ARM CPUs interfacing
with DSPs.

I will study that as i am not familiar with virtio .

Follow Ira's advice. Talk to the guys working on virtio, tell them what
you are trying to do. They'll likely have good advice for you.

Good luck!

Cheers,
Dave

Warm Regards,

S.Saravanan